ADDR02 Search Results

Contextual Info: SPACE ELECTRONICS INC. 8 MEGABIT EEPROM MCM GND I/O15 ADDR07 GND ADDR06 5V ADDR05 ADDR04 ADDR03 ADDR02 ADDR01 79LV0832RP ADDR00 GND 5V GND GND GND GND 5V GND GND GND GND I/O16 SPACE PRODUCTS 73 CE1 I/O17 I/O14 1 I/O18 I/O13 I/O19 I/O12 I/O20 I/O11 I/O21 I/O10

YMB 06

Abstract: ADDR01
Contextual Info: 8 MEGABIT EEPROM MCM SPACE ELECTRONICS INC. 79C0832RP GND ADCBUS35 ADDRESS 73 ADDR07 5V GND ADDR06 ADDR05 ADDR04 ADDR03 ADDR02 ADDR01 ADDR00 5V GND GND GND GND GND GND 5V GND ADCBUS36 GND GND SPACE PRODUCTS GROUP CE1 ADCBUS34 1 ADCBUS38 ADCBUS33 ADCBUS39 ADCBUS32

79C0832RP

Contextual Info: SPACE ELECTRONICS INC. 8 MEGABIT EEPROM MCM GND I/O15 ADDRESS CE1 73 ADDR07 GND ADDR06 5V ADDR05 ADDR04 ADDR03 79C0832RP ADDR02 ADDR01 ADDR00 GND GND 5V GND GND GND GND GND 5V GND GND I/O16 SPACE PRODUCTS I/O14 1 I/O18 I/O13 I/O19 I/O12 I/O20 I/O11 I/O21 I/O10

SuperSPARC

Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Contextual Info: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys­

SASI

Abstract: cmps a13 grd 07 z32106 Z32100 IRR28 we32100
Contextual Info: Zilog P roduct S pecification January 1987 / O D ^ O ^ Z32106 M A U M A T H A C C E L E R A T IO N U N IT DESCRIPTION T he Z32106 M ath A cceleration U nit M AU provides floating-point capability fo r the Z32100 M icroprocessor and is fully com patible with

Z32100

Abstract: z32104
Contextual Info: Zilog P r o du c t S p e c i f i c a t i o n J a n u a ry 1987 /oc€>o4 Z32104 D M A C O N TR O LL ER D ESCRIPTIO N T h e Z32104 D M A C o n tro lle r D M A C is a m em ory-m apped p e rip h e ra l device th a t p erfo rm s m em ory-to-m em ory, m em ory-to-peripheral, and

WE32100

Abstract: ALI m7 101b WE32104
Contextual Info: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a mem ory-mapped peripheral device that performs memory-to-memory, memory fill, mem ory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that

ADVANCED COMMUNICATION DEVICES

Abstract: ACD80800 ACD80900 ACD82216 ACD82224 16N03 P03R
Contextual Info: Advanced Communication Devices Corp ADVANCE INFORMATION Data Sheet: ACD82224 ACD82224 24 Ports 10/100 Fast Ethernet Switch Last Update: September 19, 2000 Please check ACD’ s website for update information before starting a design Web site: http://www.acdcorp.com

micro SD socket

Abstract: usb multi micro SD socket usb to micro SD socket mp3 player circuit diagram pro duo card XD SMC card reader TF card usb 3 sm Flash drive controller cf card diagram usb with micro SD socket
Contextual Info: 1 Data Book AU9368 USB Multi-LUN Flash Card Reader Controller Technical Reference Manual Product Specification Official Release Revision 1.19W Public Jul 2005 Data sheet status Objective specification This data sheet contains target or goal specifications for

chilled water system

Contextual Info: Data Sheet, Revision 3 September 21, 2005 TSI-2 2k x 2k Time-Slot Interchanger 1 Introduction The last issue of this data sheet was August 31, 2005. A change history is included in Section 11 Change History on page 61. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text

IVG10

Abstract: B08 REGULATOR
Contextual Info: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 a FEATURES PERIPHERALS Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory see memory information on Page 4 Each Blackfin core includes: Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

WE32101

Abstract: we32100 tC23E oxbe
Contextual Info: WE 32100 Microprocessor Description The WE 32100 Microprocessor CPU is a highperformance, single-chip, 32-bit central processing unit designed for efficient operation in a high-level language environment. It performs all the system address generation, control, memory access, and

WE32104

Abstract: we32100 DMAC
Contextual Info: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a memory-mapped peripheral device that performs memory-to-memory, memory fill, memory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that

we32100

Contextual Info: WE 32106 Math Acceleration Unit Description The WE 32106 Math Acceleration Unit MAU provides floating-point capability for the WE 32100 Microprocessor and is fully compatible with the IEEE Standard for Binary FloatingPoint Arithmetic (ANSI/IEEE Std. 754-1985). It

adn8810acpz

Abstract: AN619 AD8605 ADN8810 ADR292 ADR292ER ADR392 FDC633N REF198 ADN8810ACPZ-REEL7
Contextual Info: 12-Bit High Output Current Source ADN8810 FUNCTIONAL BLOCK DIAGRAM High precision 12-bit current source Low noise Long term stability Current output from 0 mA to 300 mA Output fault indication Low drift Programmable maximum current 24-lead 4 mm x 4 mm leadframe chip scale package

fprog 2 schematic

Abstract: A18E A17E HC12 M68HC12 MC68HC812A4 MC68HC812A4PV 32byte
Contextual Info: Advance Information This document contains information on a new product. Specifications and information herein are subject to change without notice. A G R E E M E N T MC68HC812A4 N O N - D I S C L O S U R E HC12 R E Q U I R E D Order this document by MC68HC812A4/D

ADSP-BF526BBCZ-4AX

Abstract: BF523 ADSP-BF522 ADSP-BF523 ADSP-BF524 ADSP-BF525 ADSP-BF526 ADSP-BF527 ADSP-BF527BBCZ-5A
Contextual Info: Blackfin Embedded Processor ADSP-BF522/523/524/525/526/527 Preliminary Technical Data FEATURES PERIPHERALS Up to 600 MHz high-performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of

RXD55

Abstract: RXD26
Contextual Info: Hardware Design Guide June 2004 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger STSI-144 device. Information relevant to the use of

NHI-156XX

Abstract: TAG 9031 15XXX NHI-15XX 56xx stanag 4007
Contextual Info: NATIONAL HYBRID, Inc. NHi-156XX Terminals NHi-157XX Terminals Bus Controller, Remote Terminal, Bus Monitor PCI Bus And Local Bus Host Interface User's Manual Version 2007.02.24 February 2007 The information provided in this document is believed to be accurate; however, no responsibility is assumed by NATIONAL

z32100

Abstract: LK23
Contextual Info: Zilog P ro du ct Specification January 1987 /£ > 3 0 3 3 Z32101 MEMORY MANAGEMENT UNIT DESCRIPTION T he Z32101 M emory M anagem ent U nit MMU is a 32-bit bus-structured device that provides logicalto-physical address translation, memory organization, control, and access protection for

Contextual Info: P r e l im in a r y P r o d u c t Sp e c if ic a t io n Z80189/Z8L189 G e n e r a l -P u r p o s e Em b e d d e d C o n t r o l l e r s FEATURES Part CPU UART I/O Speed MHz Z 801 89 S180* 16550 24 33 Z 8L1 89 S180* 16550 24 20 • Fully Static Z180 MPU Core*

A18E

Abstract: fprog 2 schematic MC68HC812A4CPV8 M68HC12 MC68HC812A4 MC68HC812A4PV 32byte
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MC68HC812A4 Data Sheet M68HC12 Microcontrollers MC68HC812A4/D Rev. 6, 8/2002 MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

XC4006E-PQ160

Abstract: XC4003E-PC84 1923H tektronix tek 455 osc. manual 2I28 pad-170 DFS60 X6994 6N24
Contextual Info: Development System Reference Guide Introduction NGDBuild The User Constraints UCF File Using Timing Constraints The Logical Design Rule Check MAP—The Technology Mapper LCA2NCD The Physical Constraints (PCF) File DRC—Physical Design Rule Check PAR—Place and Route

TS127 08

Abstract: RXD55 RXD01 txd45 RXD4-8 RXD35 TSI-16 RXD26 TXD38 TXD37
Contextual Info: Advance Information May 2003 TSI-16 Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. TSI-16 device. Information relevant to the use of the device in a board design is covered. Ball descriptions, dc electrical characteristics,