7C130 Search Results

CY7C1302V25

Abstract: CY7C1302V25-133BZC
Contextual Info: yy 7c1302V25: Rev 1.0 Revised: February 15, 2000 7C1302V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth

7C130

Abstract: L1314
Contextual Info: 7C130/CY7C131 CY7C140/CY7C141 _ 1024 x 8 Dual-Port Static RAM aT ^ p -¿r CYPRESS ^ SEMICONDUCTOR E ach p o rt has independent control pins; chip enable C E , w rite enable (RyW), and output The CY 7C130/CY7C131/CY7C140/ enable (O E ). TVvo flags are p rovided on each

cy7c131-55nc

Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140
Contextual Info: 7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master 7C130/CY7C131 easily ex­

ebe switches

Abstract: CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35
Contextual Info: CYPRESS SEMICONDUCTOR 00 0 3 4 2 1 EbE D 5 • 7C130/CY7C131 CY7C140/CY7C141 -Z Z A Z . o y n p rrQ C 1024 x 8 Dual-Port Static RAM SEMICONDUCTOR Features Functional Description • 0,8-micron CMOS for optimum speed/power • Automatic power-down • TTL-compatible

CY7C1304V25

Contextual Info: 5 7C1304V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time

Contextual Info: 7C130/CY7C131 CY7C140/CY7C141 CYPRESS SEMICONDUCTOR Features Functional Description • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable of withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation

Contextual Info: fax id: 5200 7C130/CY7C131 CY7C140/CY7C141 W CYPRESS 1K x 8 Dual-Port Static Ram Features Functional Description True Dual-Ported memory cells which allow simulta­ neous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power

CY7C1304V25

Contextual Info: 304V25 7C1304V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time

ATPA

Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C

PLCC-52

Abstract: CY7C130 CY7C131 CY7C140 CY7C141 CY7C131-25JC CY7C131-35J Z1014
Contextual Info: 7C130, 7C130A CY7C131, CY7C131A CY7C140, CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1K x 8 organization ■ 0.65 micron CMOS for optimum speed and power

7C13135

Abstract: CY7C140-35PC 7C130 CY7C130 CY7C131 CY7C140 CY7C141
Contextual Info: 7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The 7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports

CY7C1305V25-167BZC

Contextual Info: 7C1305V25 7C1307V25 PRELIMINARY 18-Mb Burst of 4 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports • 2.5V core power supply with HSTL Inputs and Outputs The 7C1305V25/7C1307V25 are 2.5V Synchronous

CY7C

Abstract: CY7C130 CY7C131 CY7C140 CY7C141
Contextual Info: 7C130, 7C130A CY7C131, CY7C131A 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power

CY7C1304V25

Contextual Info: 7C1304V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167 MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time • 4-Word burst for reducing address bus frequency

Contextual Info: 7C1302V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time

CY7C130

Abstract: CY7C131 CY7C140 CY7C141
Contextual Info: 7C130, 7C130A CY7C131, CY7C131A 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power

Contextual Info: 7C130/CY7C131 _ CY7C140/CY7C141 = SEMICONDUCTOR 1024 x 8 D ual-Port Static R A M Features Functional Description • 0.8-micron CMOS for optimum speed/power T he CY 7C 130/CY7C13 L/CY7C140/ CY7C141 arc high-speed C M O S IK by 8 dual-port static RA M s. Two ports are pro­

96182

Abstract: 9715 cy7c136
Contextual Info: Cypress Semiconductor Qualification Report QTP# 97045/97154 VERSION 1.1 April, 1997 Dual Port SRAM - R28 Technology 7C130/131 1K x 8 Dual Port SRAM CY7C140/141 1K x 8 Dual Port SRAM CY7C132/136 2K x 8 Dual Port SRAM CY7C142/146 2K x 8 Dual Port SRAM Cypress Semiconductor

Contextual Info: 7C130 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power

CY7C1305V25-167BZC

Abstract: CY7C1305V25 CY7C1307V25
Contextual Info: 1305V25 7C1305V25 7C1307V25 Preliminary 18 Mb Burst of 4 Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time

CY7C130

Abstract: CY7C131 CY7C140 CY7C141
Contextual Info: 7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns

CY7C1304V25

Contextual Info: 5 7C1304V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time

CY7C136E

Abstract: CY7C131AE-15JXI CY7C136AE-55NXI
Contextual Info: CY7C131E, CY7C131AE CY7C136E, CY7C136AE 1 K / 2 K x 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization

C1307

Abstract: cY7c131 I CY7C130 CY7C131 CY7C140 CY7C141 C130-15 C1303 C13017
Contextual Info: fax id: 5200 1CY 7C14 0 7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static Ram Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power