BB165A Search Results

BB209

Abstract: BB100 BB484 165 BALL FBGA BB42 bb209a 288-ball 676-BALL BB165B
Contextual Info: Package Diagrams Thin Ball Grid Array Packages 42-Ball Thin Ball Grid Array 6 x 5 x 1.2 mm BB42 51-85139-*A 1 Package Diagrams 100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100 51-85107-*B 2 Package Diagrams 165-Ball FBGA (13 x 15 x 1.2 mm) BB165A 51-85122-*B

CY7C1386C

Abstract: CY7C1387C
Contextual Info: CY7C1386C CY7C1387C 18-Mb 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

CY7C1381B-100AI

Abstract: 381B CY7C1381B CY7C1381B-117AC CY7C1383B
Contextual Info: 381B CY7C1381B CY7C1383B 512 x 36/1M × 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 10.0 ns Fast clock speed: 117, 100, 83 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion

1382C

Contextual Info: 380C CY7C1380C CY7C1382C PRELIMINARY 512K x 36 / 1M x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns

CY7C1381c-100ac

Contextual Info: 381C CY7C1381C CY7C1383C PRELIMINARY 512K x 36/1M x 18 Flow-Thru SRAM Features • • • • • • • • • • • • Fast access times: 6.5, 7.5, 8.5 ns Fast clock speed: 133, 117, 100 MHz Provide high-performance 2-1-1-1 access rate Optimal for depth expansion

Contextual Info: CY7C1371C CY7C1373C 18-Mb 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero

CY7C136B

Contextual Info: CY7C1360B CY7C1362B PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.

Contextual Info: CY7C1317V18 CY7C1319V18 CY7C1321V18 PRELIMINARY 18-Mb DDR -II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mb density 2M x 8, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency

1382C

Contextual Info: CY7C1380C CY7C1382C 512K x 36/1M x 18 Pipelined SRAM Features Functional Description • Fast clock speed: 250, 225, 200, 167, 133 MHz • Provide high-performance 3-1-1-1 access rate • Fast OE access times: 2.6, 2.8, 3.0, 3.4, 4.2ns • Optimal for depth expansion

Contextual Info: CY7C1361B CY7C1363B 9-Mb 256K x 36/512K x 18 Flow-Through SRAM Functional Description[1] Features • • • • • Supports 133-MHz bus operations 256K X 36/512K X 18 common I/O 3.3V –5% and +10% core power supply (VDD) 2.5V or 3.3V I/O supply (VDDQ)

Contextual Info: CY7C1360B CY7C1362B 9-Mb 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 225 MHz • Available speed grades are 225, 200 and 166 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply

Contextual Info: CY7C1370CV25 CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No

CY7C1305V25-167BZC

Contextual Info: CY7C1305V25 CY7C1307V25 PRELIMINARY 18-Mb Burst of 4 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports • 2.5V core power supply with HSTL Inputs and Outputs The CY7C1305V25/CY7C1307V25 are 2.5V Synchronous

CY7C1311V18

Abstract: CY7C1313V18 CY7C1315V18
Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 PRELIMINARY 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • Four-word Burst for reducing address bus frequency

CY7C1304V25

Contextual Info: CY7C1304V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167 MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time • 4-Word burst for reducing address bus frequency

CY7C1370B

Abstract: CY7C1372B
Contextual Info: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate

CY7C1386CV25

Abstract: CY7C1387CV25
Contextual Info: CY7C1386CV25 CY7C1387CV25 18-Mb 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1355B CY7C1357B 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero

CY7C1371

Abstract: CY7C1371B CY7C1373 CY7C1373B
Contextual Info: CY7C1371B CY7C1373B 73B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock

Contextual Info: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate

Contextual Info: CY7C1302V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time

CY7C1360B

Abstract: CY7C1362B
Contextual Info: CY7C1360B CY7C1362B 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 225 MHz • Available speed grades are 225, 200 and 166 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply

CY7C1311V18

Abstract: CY7C1313V18 CY7C1315V18
Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency

CY7C1370CV25

Abstract: CY7C1370CV25-167 CY7C1370CV25-200 CY7C1370CV25-225 CY7C1370CV25-250 CY7C1372CV25 CY7C1372CV25-225 CY7C1372CV25-250
Contextual Info: CY7C1370CV25 CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No