CY7C1370B Search Results

CY7C1370B

Abstract: CY7C1372B
Contextual Info: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate

Contextual Info: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate

CY7C1370BV25-167AC

Abstract: CY7C1370BV25 CY7C1372BV25
Contextual Info: CY7C1372BV25 CY7C1370BV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200,167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, 4.2 ns • Internally synchronized registered outputs eliminate

CY7C1370B

Abstract: CY7C1370B-133AC CY7C1372B
Contextual Info: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate

TMS 3766

Abstract: DPA 51 7C1370
Contextual Info: 1CY7C1372BV25 CY7C1370BV25 CY7C1372BV25 PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 180,166, 150, and 133 MHz • Fast access time: 3.0,3.2,3.4, 3.8, 4.2 ns

CY7C1370B

Abstract: CY7C1372B 5A- BGA MHZ
Contextual Info: CY7C1370B CY7C1372B PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 166, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, 4.2 ns

CY7C1370B-133AC

Abstract: 372B CY7C1370B CY7C1370B-200AC CY7C1372B
Contextual Info: 372B CY7C1370B CY7C1372B PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, 4.2 ns

CY7C1370B-133BZC

Contextual Info: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate

CY7C1370BV25

Abstract: CY7C1372BV25
Contextual Info: CY7C1372BV25 CY7C1370BV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200,167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, 4.2 ns • Internally synchronized registered outputs eliminate

CY7C1370BV25

Abstract: CY7C1372BV25
Contextual Info: 372BV25 CY7C1370BV25 CY7C1372BV25 PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • No Bus Latency NoBLTM , no dead cycles between write and read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, 4.2 ns

T1X15

Abstract: CY7C9536B CYS25G0101DX OIF-SPI3-01 TRS-X
Contextual Info: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997

vhdl code for dice game

Abstract: Video Proc 3.3V 0.07A 64-Pin PQFP ez811 GRAPHICAL LCD interfaced with psoc 5 cypress ez-usb AN2131QC CYM9239 vhdl code PN 250 code generator CY3649 cy7c63723 Keyboard and Optical mouse program CY7C9689 ethernet
Contextual Info: Product Selector Guide Communications Products Description Pins Part Number Freq. Range Mbps ICC (mA) Packages* 3.3V SONET/SDH PMD Transceiver 2.5V SiGe Low Power SONET/SDH Transceiver SONET/SDH Transceiver w/ 100K Logic 2.5 G-Link w/ 100K Logic OC-48 Packet Over SONET (POS) Framer

CY7C1370B

Abstract: CY7C1370C CY7C1372C
Contextual Info: CY7C1370C CY7C1372C PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between write and read cycles • Fast clock speed: 250, 225, 200, and 167 MHz • Fast access time: 2.6, 2.8, 3.0, 3.4 ns

CY7C9538

Abstract: CYS25G0101DX cypress 1994 sram zero concatenated and OC-3 and STM-1 3C6V 1xVC4-16c T1X15
Contextual Info: CONFIDENTIAL CY7C9538 OC-48/STM-16 Framer with Reconfigurable VC–POSIC2GVC-R Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Programmable frame tagging engine for packet preclassification enables such features as

Contextual Info: CY7C1370C CY7C1372C PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between write and read cycles • Fast clock speed: 250, 225, 200, and 167 MHz • Fast access time: 2.6, 2.8, 3.0, 3.4 ns

DQ214

Abstract: CY39100V388-200MGC CY7C1370B CYS25G0101DX MPC860 MSM7717-01 XCVE-600 pA2240 prbs parity checker and generator RDAT10
Contextual Info: 10, 3610 PRELIMINARY CY7C9536-EVAL POSIC Evaluation Board Introduction Standard MICTOR connectors are used on all buses for external driving and observing signals.This permits the user to directly control all aspects of the board’s operation. Purpose

nobl sram 1994

Abstract: CY7C9536B-BLC CY7C9536B CYS25G0101DX VC45V
Contextual Info: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997

CY7C1338-100AXC

Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
Contextual Info: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12

mictor

Abstract: mictor connector board data Mictor 38 connecter cyp15g0401dx cypress cpld hotlink Mictor connecter CY39100V388-200MGC CY7C1370B CYS25G0101DX MPC860
Contextual Info: CYPOSIC2GVC-K PRELIMINARY POSIC2GVC /POSIC2G™ Evaluation Board Purpose This board is intended for two purposes. The first is as a demonstration of the capabilities of the Packet-Over-SONET Integrated Circuit POSIC2GVC device. The second is as a development platform for the system designer who wants to

T1X15

Abstract: CY7C9536B-BLC cfk logic chip CY7C9536B CYS25G0101DX
Contextual Info: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997

Contextual Info: CY7C1370CV25 CY7C1372CV25 PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between write and read cycles • Fast clock speed: 250, 225, 200, and 167 MHz • Fast access time: 2.6, 2.8, 3.0, 3.4 ns

Cp5609amt

Abstract: cp5858am CP5629BM CG5113 PCN030073 W48S111-14G 5L512 CY2292ASI CY2292SL-1V1 CY2292SC-68T
Contextual Info: SEMICONDUCTOR FINAL PRODUCT CHANGE NOTIFICATION PCN: PCN030073 DATE: November 7, 2003 Subject: Prune List Q4, 2003 To: Description of Change: Cypress is officially announcing the obsolescence of these products. Refer to the attached list for the list of products being discontinued.

CY7C1370C

Abstract: CY7C1370CV25 CY7C1372C CY7C1372CV25 CY7C1372CV25-200BZC
Contextual Info: CY7C1370CV25 CY7C1372CV25 PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between write and read cycles • Fast clock speed: 250, 225, 200, and 167 MHz • Fast access time: 2.6, 2.8, 3.0, 3.4 ns

SDH 209

Abstract: 1xVC4-16c CY7C9538 CYS25G0101DX VC45V
Contextual Info: CONFIDENTIAL CY7C9538 OC-48/STM-16 Framer with Reconfigurable VC–POSIC2GVC-R Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Programmable frame tagging engine for packet preclassification enables such features as