RXD13 Search Results

MC 4011 BCP

Abstract: PKT 4113 API ncp 6131 SWITCHING SYSTEMS INTERNATIONAL sqm 225 leach 1522 her 4541 MSP SNCP t 1451 n 52 toh SWITCHING SYSTEMS INTERNATIONAL sqm 350 k2400 EQUIVALENT
Contextual Info: EtherPHAST -24 Device 2x OC-12/STM-4 SONET/SDH Ethernet Mapper TXC-06745 DATA SHEET TXC-06745-MB, Ed. 2 February 2006 FEATURES APPLICATIONS • Client Interfaces: 2x GMII/24x SMII/4x TBI/MPI 24 channel packet all pin shared • Two serial Gigabit Ethernet (1.25 Gbit/s) ports with integrated CRSU/SerDes (8B/10B)

Cx2829

Abstract: ,national semiconductor Linear brief lb-3
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

Contextual Info: TLK2501 1.5 TO 2.5 GBPS TRANSCEIVER SLLS427D − AUGUST 2000 − REVISED JULY 2003 D Hot-Plug Protection D 1.5 to 2.5 Gigabits Per Second Gbps Serializer/Deserializer D High-Performance 64-Pin VQFP Thermally D D D D Enhanced Package (PowerPAD) 2.5-V Power Supply for Low Power

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98431 10/100 Mbps Ethernet TM CONTROLLER DESCRIPTION The µPD98431 is a 10/100 Mbps Ethernet controller having eight Media Access Control MAC ports conforming to IEEE 802.3 and IEEE 802.3u. Each port can store 1 packet of receive data since each port has a 2 KB receive FIFO. This can reduce the

Contextual Info: TLK3118 Redundant XAUI Transceiver www.ti.com • • • • • • • • • • • Fabricated in Advanced 130-nm CMOS Technology Package: Small Footprint 21x21mm, 400-Ball, Fine Pitch 1mm PBGA TLK3118 TDP/N[3:0]0 TCLK TD(31.0) TC(3.0) RCLK RD(31.0)

56-PIN

Abstract: AFE1105 AFE1115 AFE1115E E1784
Contextual Info: AFE 111 AFE1115 ® 5 HDSL/MDSL ANALOG FRONT END WITH VCXO ● +5V ONLY 5V or 3.3V Digital ● SCALEABLE DATA RATE ● 300mW POWER DISSIPATION FEATURES ● COMPLETE HDSL ANALOG INTERFACE ● E1, T1 AND MDSL OPERATION ● 56-PIN SSOP ● VCXO AND VCXO CONTROL CIRCUITRY

48-PIN

Abstract: AFE1103 AFE1103E
Contextual Info: AFE AFE1103 110 3 HDSL/MDSL ANALOG FRONT END FEATURES DESCRIPTION ● COMPLETE ANALOG INTERFACE Burr-Brown’s Analog Front End greatly reduces the size and cost of an HDSL or MDSL system by providing all of the active analog circuitry needed to connect

Contextual Info: TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER SLLS428F − JUNE 2000 − REVISED JANUARY 2004 D Hot Plug Protection D 0.6 to 1.5 Gigabits Per Second Gbps Serializer/Deserializer D High-Performance 64-Pin VQFP Thermally D D D D Enhanced Package (PowerPAD) 2.5 V Power Supply for Low Power

Contextual Info: TLK2521 1.0 to 2.5 Gbps 18ĆBIT SERDES SLLS574D − JULY 2003 − REVISED JULY 2007 Serializer/Deserializer D High-Performance 64-Pin HTQFP Thermally D D D D D D D D D Applications On-chip PLL Provides Clock Synthesis From Low-Speed Reference Receiver Differential Input Thresholds

R14 P1F

Abstract: N-333 PP7F 1BE3 P53 transistor A1-U1-U17-A17 3LH30 zz12
Contextual Info: TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CF26AXBG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. TMP92CF26A

pfc8574

Abstract: ENC 03 LTC2272 marking code s4 diode op amp marking P3 JESD204 LTC2273
Contextual Info: LTC2273/LTC2272 16-Bit, 80Msps/65Msps Serial Output ADC DESCRIPTION FEATURES n High Speed Serial Interface JESD204 Sample Rate: 80Msps/65Msps 77.7dBFS Noise Floor 100dB SFDR SFDR >90dB at 140MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P or 1.5VP-P Input Range)

Contextual Info: TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649A – AUGUST 2000 – REVISED FEBRUARY 2001 D D D D D D Hot-Plug Protection 2.5 Gigabits to 3.125 Gigabits Per Second Gbps Serializer/Deserializer High Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD)

IR10D

Abstract: RPS_PRES HY514264 R1799-2 TPI-10 74f04d 980b bergstik ARB12 mst12
Contextual Info: LXD980/980B Reference Design Schematics Reference Design Schematics Reference Design Schematic, Sheet 1:LXD 980 Top Level Schematic
 D-1 LXD980/980B Reference Design Users Guide Reference Design Schematic, Sheet 2:Raptor1 1 2 IR10DAT IR10CLK IR10ENA IR10DEN

Contextual Info: Preliminary Data Sheet August 1998 microelectronics group Lucent Technologies Bell Labs Innovations TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger Features Applications • Thirty-two full-duplex, serial time-division multi­ plexed TDM highways.

Contextual Info: B U R R -B R O W N AFE1115 HDSL/MDSL ANALOG FRONT END WITH VCXO FEATURES • • • • • COMPLETE HDSL ANALOG INTERFACE • E1, T1 AND MDSL OPERATION • VCXO AND VCXO CONTROL CIRCUITRY +5V ONLY 5V or 3.3V Digital SCALEABLE DATA RATE 300mW POWER DISSIPATION

Contextual Info: B U R R -B R O W N AFE1203 2Mbps, Single Pair HDSL ANALOG FRONT END FEATURES • • • • • • • • E1/T1 SINGLE PAIR 2B1Q OPERATION COMPLETE ANALOG INTERFACE 385mW POWER DISSIPATION PROGRAMMABLE POWER 48-LEAD SSOP PACKAGE SCALEABLE DATA RATE OPERATION FROM 2.3Mbps TO 160kbps

SMD codes

Abstract: 063310
Contextual Info: QuadPHY 10GX ASSP Telecom Standard Product Data Sheet Released PM8358 QuadPHY® 10GX 4 X 1.2 to 3.2 Gbit/s Quad, Fully Redundant, XAUI to XGMII, 10 Gigabit Ethernet / Fibre Channel Physical Layer Device Data Sheet Released Issue No. 5: April 2004 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

sony rxd7

Abstract: w1p13 XMT 2315 8B10B RXD14 3156 00010001
Contextual Info: 8101 8101 Gigabit Ethernet Controller 99110 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, access

Inter-ICs

Abstract: chn 940 S1C33L01 1431T dot led display large size with circuit diagram YUV411 i781symbol LUT43 S1C33L19 786LCD
Contextual Info: S1C33L19 Technical Manual CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S1C33L19 Technical Manual S1C33L19 Technical Manual SEMICONDUCTOR OPERATIONS DIVISION EPSON Electronic Devices Website http://www.epson.jp/device/semicon_e Document code: 411664200 April 2009 in JAPAN D

S1C33L17

Abstract: S1C33L17D S1C33L17F Inter-ICs dot led display large size with circuit diagram LOT code stmicroelectronics S1C33L01 S1C33L17B 2451c BT 342 project
Contextual Info: S1C33L17 Technical Manual CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S1C33L17 Technical Manual S1C33L17 Technical Manual SEMICONDUCTOR OPERATIONS DIVISION EPSON Electronic Devices Website http://www.epson.jp/device/semicon_e Document code: 411520600 Fist issue June, 2008 C B

bv228

Abstract: S1C33210 S1C33L01 MF1517-01 CP4D
Contextual Info: MF1517-01 CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S1C33210 Technical Manual S1C33210 PRODUCT PART S1C33210 FUNCTION PART NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

TD15

Abstract: TLK2500 TLK2500IRCP
Contextual Info: TLK2500IRCP 1.6 Gbps to 2.5 Gbps TRANSCEIVER SLLS356B – JUNE 1999 – REVISED JANUARY 2000 D D D D D D D 1.6 to 2.5 Gigabits Per Second Gbps Serializer/Deserializer Hot Plug Protection High-Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD)

DIGITAL ECHO pcb

Abstract: 48-PIN AFE1105 AFE1105E AFE1105EA
Contextual Info: AFE AFE1105 110 5 HDSL/MDSL ANALOG FRONT END FEATURES DESCRIPTION ● COMPLETE ANALOG INTERFACE ● T1, E1, AND MDSL OPERATION Burr-Brown’s Analog Front End greatly reduces the size and cost of an HDSL or MDSL system by providing all of the active analog circuitry needed to connect

LFBGA-233

Abstract: GL9711 BCN18 CH-610 101 R15 N 101 JT genesys PCI-Express 2.0 X8 connector Pinout smd diode code T9 smd diode K10 BCN158
Contextual Info: Genesys Logic, Inc. GL9711 PCI ExpressTM PIPE x1 PHY Datasheet Revision 1.10 Jul. 04, 2006 GL9711 PCI ExpressTM PIPE x1 PHY Copyright: Copyright 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc.