CY7C Search Results

bzx 850

Abstract: bzx 850 30
Contextual Info: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state

CY7C09449PVA-AC

Abstract: 8c04 i486 PC MOTHERBOARD CIRCUIT diagram
Contextual Info: CY7C09449PVA-AC 128 Kb Dual-Port SRAM with PCI Bus Controller PCI-DP Features Functional Overview • 128 Kb of dual-ported shared memory ■ Master and target PCI Specification 2.2 compliant interface ■ Embedded host bridge capability ■ Direct interface to many microprocessors

Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

CY7C1059DV33

Abstract: CY7C1059DV33-10BAXI CY7C1059DV33-10ZSXI
Contextual Info: PRELIMINARY CY7C1059DV33 8-Mbit 1M x 8 Static RAM Functional Description[1] Features • High speed — tAA = 10 ns The CY7C1059DV33 is a high-performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an

9l reset

Abstract: CY7C0852V-133AC CY7C09289V CY7C09369V CY7C09379V
Contextual Info: CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features Functional Description

Cypress VMEbus Interface Handbook

Abstract: Cypress Applications Handbook 64 pin CERAMIC QUAD FLATPACK 64-pin CERAMIC QUAD FLATPACK CY7C964-ASC G68 Package CY7C960 CY7C961 CY7C964 VIC068A
Contextual Info: 64 CY7C964 Bus Interface Logic Circuit Features • Comparators, counters, latches, and drivers minimize logic requirements for a variety of multiplexed and non-multiplexed buses • Directly drives VMEbus address and data signals • 8-bit comparator for slave address decoding

cypress flash 370

Abstract: logic block diagram of cypress flash 370 device 22v10 CY7C375 FLASH370 o112i cypress flash 370 CPLD cypress flash 370 device technology
Contextual Info: fax id: 6130 For new designs see CY7C375i CY7C375 UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 28 macrocells in eight logic blocks • 28 I/O pins • 6 dedicated inputs including 4 clock pins • Bus Hold capabilities on all I/Os and dedicated inputs

CY7C187

Abstract: CY7C187A
Contextual Info: CY7C187A 64K x 1 Static RAM Features provided by an active LOW chip enable CE and three-state drivers. The CY7C187A has an automatic power-down feature, reducing the power consumption by 55% when deselected. • High speed — 20 ns • CMOS for optimum speed/power

C2665

Abstract: C2668 7c26 C2662 C266 27C64 CY7C266 R1250 C2666
Contextual Info: 1CY 7C26 6 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial)

CY7C161

Abstract: CY7C162 C1624
Contextual Info: CY7C161 CY7C162 16K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enables CE1, CE2 and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 65% when deselected.

7C344-25

Abstract: C344 74HC CY7C344 Signal Path Designer C3445
Contextual Info: CY7C344 32-Macrocell MAX EPLD Features tional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the

CY7C1339

Contextual Info: fax id: 1109 PRELIMINARY CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

C1507

Abstract: C1504 C1502 c1509 C150 CY7C150 R1329
Contextual Info: CY7C150 1Kx4 Static RAM Features Separate I/O paths eliminates the need to multiplex data in and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset, deselect, or when output enable OE is held HIGH, allowing for

C401 diode

Abstract: 10DC IR transistor 10dc ir C4016 C4019 C401 CY7C401 CY7C402 CY7C403 C4013
Contextual Info: CY7C401/CY7C403 CY7C402/CY7C404 64 x 4 Cascadable FIFO 64 x 5 Cascadable FIFO Features words. Both the CY7C403 and CY7C404 have an output enable OE function. • 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO)

CY7C4255V

Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V
Contextual Info: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to

CY7C128A

Abstract: transistor C128 C128A 7C128A-45 7C128A-25
Contextual Info: 1CY 7C12 8A CY7C128A 2K x 8 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 440 mW commercial — 550 mW (military) • Low standby power

64KX32

Abstract: 7C1334-100 7C1334-133 7C1334-50 7C1334-80 CY7C1334
Contextual Info: fax id: 1084 CY7C1334 PRELIMINARY 64Kx32 Pipelined SRAM with NoBL Architecture Features • Low 16.5 mW standby power Functional Description • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32P • Supports 133-MHz bus operations with zero wait states

SMPTE-125M

Abstract: nrzi encoder 8b/10b scrambler CY7B9234 CY7C9235 259M-BCD
Contextual Info: PRELIMINARY CY7C9235 SMPTE-259M/DVB-ASI Scrambler-Controller Features a CY7B9234 HOTLink transmitter, which then converts the bit-parallel characters into a SMPTE-259M compatible high-speed serial data stream. • Fully compatible with SMPTE-259M-BCD — SMPTE-125M compliant for 4:2:2 component video

CY7C4205V

Abstract: CY7C4215V CY7C4225V CY7C4235V CY7C4245V CY7C42X5V CY7C4425V
Contextual Info: fax id: 5417 CY7C4425V/4205V/4215V PRELIMINARY CY7C4225V/4235V/4245V 64/256/512/1K/2K/4K x18 Low Voltage Synchronous FIFOs Features • 3.3V operation for low power consumption and easy integration into low voltage systems • High-speed, low-power, first-in first-out FIFO

C167A-3

Abstract: C167A-2 CY7C167A CY7C167A-35DMB cy7c167a-35pc
Contextual Info: CY7C167A 16K x 1 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 275 mW • Low standby power — 83 mW • TTL-compatible inputs and outputs

IDT709079

Abstract: IDT709089
Contextual Info: 025/0251 CY7C09079/89/99 CY7C09179/89/99 PRELIMINARY 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices — 32K x 8/9 organizations CY7C09079/179

Contextual Info: CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins

CY7C1020

Contextual Info: Y7C10 PRELIMINARY CY7C1020 32K x 16 Static RAM Features BLE is LOW, then data from I/O pins (I/O 1 through I/O8), is written into the location specified on the address pins (A0 through A 14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14).