CY7C13 Search Results

Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state

Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

CY7C1339

Contextual Info: fax id: 1109 PRELIMINARY CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

64KX32

Abstract: 7C1334-100 7C1334-133 7C1334-50 7C1334-80 CY7C1334
Contextual Info: fax id: 1084 CY7C1334 PRELIMINARY 64Kx32 Pipelined SRAM with NoBL Architecture Features • Low 16.5 mW standby power Functional Description • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32P • Supports 133-MHz bus operations with zero wait states

64KX32

Abstract: 7C13 CY7C1329
Contextual Info: fax id: 1080 1CY 7C13 29 CY7C1329 PRELIMINARY 64K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1329 is 3.3V 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

80486 microprocessor block diagram and pin diagram

Abstract: 64KX32 CY7C1336
Contextual Info: 36 PRELIMINARY CY7C1336 64K x 32 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description • Supports 66-MHz microprocessor cache systems with zero wait states • 64K by 32 common I/O • Low Standby Power 1.65 mW, L version • Fast clock-to-output times

CY7C1350

Abstract: IDT71V546 MCM63Z736
Contextual Info: fax id: 1103 CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V546, MT55L128L36P and MCM63Z736 • Supports 143-MHz bus operations with zero wait

7C1351-40

Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737
Contextual Info: fax id: 1102 CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states

7C13

Abstract: CY7C1335
Contextual Info: fax id: 1045 1CY 7C13 35 PRELIMINARY CY7C1335 32K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 660 µW standby power (f=0, L version) The CY7C1335 is 3.3V 32K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

CY7C1361V25

Abstract: CY7C1363V25
Contextual Info: C Y 7 C 1 3 6 1 V 25 C Y 7 C 1 3 6 3 V 25 PRELIMINARY ~= C Y P H hbb = 256K x 36 / 512K x 18 Flowthrough SRAM Functional Description Features • Supports 113-MHz bus operations The CY7C1361V25 and CY7C1363V25 are 2.5v, 256K x 36 and 512K x 18 synchronous-flowthrough SRAM designed to

CY7C1355C

Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

m3351

Abstract: KD 2114 marking code J2UT 1203 6d t201 CY7C1339 EQUIVALENT cd 1031 cs
Contextual Info: CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features The CY7C1339 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when V DDq=2.5V. * Supports 100-MHz bus fo r Pentium and PowerPC operations w ith zero w ait states

cy7c131-55nc

Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140
Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex­

CY7C1347

Abstract: CY7C1347-166AC
Contextual Info: CY7C1347 V CYPRESS 128K X 36 Synchronous-Pipelined Cache RAM T he CY7C1347 I/O pins can operate at eith e r the 2.5V or the 3.3V level, the I/O pins are 3.3V to le ra n t w h en V ddq =2.5V. Features • S u p p o rts 1 0 0-M H z bus fo r Pentium o p e ratio n s w ith zero w ait sta tes

ebe switches

Abstract: CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35
Contextual Info: CYPRESS SEMICONDUCTOR 00 0 3 4 2 1 EbE D 5 • CY7C130/CY7C131 CY7C140/CY7C141 -Z Z A Z . o y n p rrQ C 1024 x 8 Dual-Port Static RAM SEMICONDUCTOR Features Functional Description • 0,8-micron CMOS for optimum speed/power • Automatic power-down • TTL-compatible

INTEL 80,82

Abstract: intel 80.82 intel 8082 INTEL 80-82 CY7C1325 ASYNCHRONOUS COUNTER
Contextual Info: CYPRESS CY7C1325 256K x 18 Synchronous 3.3V Cache RAM Features Functional Description • Supports 117-M Hz microprocessor cache systems with zero wait states • 256K by 18 common I/O • Fast ciock-to-output times — 7.5 ns 117-M Hz version • Two-bit wrap-around counter supporting either inter­

Contextual Info: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth

CY7C1382DV33-200BZI

Contextual Info: CY7C1380DV33 CY7C1382DV33 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades is 200 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1352G 4-Mbit 256 K x 18 Pipelined SRAM with NoBL Architecture 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

CY7C1352

Abstract: MCM63Z818 MCM63Z819
Contextual Info: CY7C1352 CY7C1352 256K x18 Pipelined SRAM with NoBL Architecture Features • Low standby power Functional Description • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z818 and MT55L256L18P • Supports 143-MHz bus operations with zero wait states

CY7C1304V25

Contextual Info: 5 CY7C1304V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time

CY7C1352B-100AC

Abstract: cy7c1352b-166ac CY7C1352B MCM63Z818 MCM63Z819 1352B-2
Contextual Info: PRELIMINARY CY7C1352B 256K x18 Pipelined SRAM with NoBL Architecture • Low standby power Features Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of

Contextual Info: fax id: 1084 W CYPRESS CY7C1334 PRELIMINARY 64Kx32 Pipelined SRAM with NoBL Architecture Features Functional Description • S u p p o rts 13 3 -M H z b u s o p e ratio n s w ith zero w ait sta tes— D ata is tra n s ferred on ev e ry clo ck T he C Y 7 C 1 334 is a 3.3V 64K by 32 syn ch ron ous-p ip eline d