CY7C136 Search Results

Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state

CY7C1361V25

Abstract: CY7C1363V25
Contextual Info: C Y 7 C 1 3 6 1 V 25 C Y 7 C 1 3 6 3 V 25 PRELIMINARY ~= C Y P H hbb = 256K x 36 / 512K x 18 Flowthrough SRAM Functional Description Features • Supports 113-MHz bus operations The CY7C1361V25 and CY7C1363V25 are 2.5v, 256K x 36 and 512K x 18 synchronous-flowthrough SRAM designed to

Contextual Info: fax id: 5201 CY7C132/CY7C136 CY7C142/CY7C146 W CYPRESS 2Kx8 Dual-Port Static RAM Features Functional Description True Dual-Ported memory cells which allow sim ulta­ neous reads of the same mem ory location 2K x 8 organization 0.65-micron CMOS for optimum speed/power

Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-raicron CMOS for optimum speed/power • BÜSŸ output flag on CY7C132/ CY7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY 7C136/CY7C142/

Contextual Info: CY7C1361A CY7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0ns Fast clock speed: 150, 133, 117, and 100MHz Fast OE access times: 3.5 ns and 4.0 ns

CY7C1360C-250BGC

Abstract: CY7C1360C CY7C1362C CY7C1360C-166BZI
Contextual Info: CY7C1360C CY7C1362C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz

Contextual Info: CY7C1361C CY7C1363C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed

CY7C132

Abstract: CY7C136 CY7C146
Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports

CY7C1362A

Abstract: GVT71512D18
Contextual Info: CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz

CY7C136-55NI

Abstract: cy7c136 CY7C132 CY7C142 CY7C146 CY7C146-15NC CY7C136-25JXC CY7C136-55NC
Contextual Info: CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 2K x 8 organization ■ 0.65 micron CMOS for optimum speed and power

CY7C1361C

Abstract: CY7C1363C
Contextual Info: CY7C1361C CY7C1363C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM Functional Description[1] Features • Supports 100, 133-MHz bus operations • Supports 100-MHz bus operations (Automotive) • 256K x 36/512K × 18 common I/O • 3.3V –5% and +10% core power supply (VDD)

A101

Abstract: CY7C1339F CY7C1364B CY7C1364B-166AC
Contextual Info: CY7C1364B 9-Mb 256K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x 32 common I/O architecture • 3.3V core power supply • 3.3V I/O operation • Fast clock-to-output times

Z1213

Abstract: CY7C132 CY7C136 CY7C146 zl12
Contextual Info: bSE » CYPRESS SEMICONDUCTOR SSÖ'lbbE 0 0 0 ^ 7 4 7 ISb I CYP CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM output enable OE . BUSY flags are pro­ vided on each port. In addition, an interrupt Functional Description Features

Contextual Info: CY7C1365C 9-Mb 256K x 32 Flow-Through Sync SRAM Functional Description[1] Features • 256K x 32 common I/O • 3.3V core power supply • 2.5V/3.3V I/O power supply • Fast clock-to-output times — 6.5 ns (133-MHz version) — 8.5 ns (100-MHz version)

Contextual Info: CY7C1365C 9-Mb 256K x 32 Flow-Through Sync SRAM Functional Description[1] Features • 256K x 32 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 8.5 ns (100-MHz version)

GVT71256B36TA-7

Abstract: GVT71256B36T-7 CY7C1361A-100AI
Contextual Info: 361A CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Flowthrough Burst SRAM Features • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip

CY7C136B

Contextual Info: CY7C1360B CY7C1362B PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.

CY7C1360C-166BZI

Abstract: CY7C1360C166BZI
Contextual Info: CY7C1360C CY7C1362C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz

Contextual Info: CY7C1361B CY7C1363B 9-Mb 256K x 36/512K x 18 Flow-Through SRAM Functional Description[1] Features • • • • • Supports 133-MHz bus operations 256K X 36/512K X 18 common I/O 3.3V –5% and +10% core power supply (VDD) 2.5V or 3.3V I/O supply (VDDQ)

Contextual Info: CY7C1360B CY7C1362B 9-Mb 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 225 MHz • Available speed grades are 225, 200 and 166 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply

CY7C1363C-133AJXI

Contextual Info: CY7C1361C, CY7C1363C 9-Mbit 256 K x 36/512 K × 18 Flow-Through SRAM 9-Mbit (256 K × 36/512 K × 18) Flow-through SRAM Features Functional Description • Supports 100 MHz, 133 MHz bus operations ■ Supports 100 MHz bus operations (Automotive) ■ 256 K × 36/512 K × 18 common I/O

b1l3

Abstract: CV7C136 CY7C1361V25 CY7C1363V25 CY7C1365V25 7C1361-133
Contextual Info: ^ _ 5r^ C Y P R F .S S CY7C1361V25 CY7C1363V25 CY7C1365V25 PBEUm m m 256K x36/256K x 32/512K x 18 Flowthrough SRAM Features • Supports 113-MHz bus operations • 256K x 36 / 256K x 32/512K x 18 common I/O » Fast clock-to-output times — 7.5 ns lor 117-MHz device

Contextual Info: CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

CY7C1360

Abstract: CY7C1360V25 CY7C1362V25 CY7C1364V25 intel 80.82
Contextual Info: CY7C1360V25 CY7C1362V25 CY7C1364V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device