7C136 Search Results

Contextual Info: CY7C132/7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-raicron CMOS for optimum speed/power • BÜSŸ output flag on CY7C132/ 7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY 7C136/CY7C142/

HA 13645

Abstract: acr38
Contextual Info: CY7C132/7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-micron CM OS for optimum speed/power • BUSY output flag on CY7C132/ 7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY 7C136/CY7C142/

CY7C1361V25

Abstract: CY7C1363V25
Contextual Info: C Y 7 C 1 3 6 1 V 25 C Y 7 C 1 3 6 3 V 25 PRELIMINARY ~= C Y P H hbb = 256K x 36 / 512K x 18 Flowthrough SRAM Functional Description Features • Supports 113-MHz bus operations The 7C1361V25 and 7C1363V25 are 2.5v, 256K x 36 and 512K x 18 synchronous-flowthrough SRAM designed to

Contextual Info: fax id: 5201 CY7C132/7C136 CY7C142/CY7C146 W CYPRESS 2Kx8 Dual-Port Static RAM Features Functional Description True Dual-Ported memory cells which allow sim ulta­ neous reads of the same mem ory location 2K x 8 organization 0.65-micron CMOS for optimum speed/power

Contextual Info: 7C1361A 7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0ns Fast clock speed: 150, 133, 117, and 100MHz Fast OE access times: 3.5 ns and 4.0 ns

CY7C132

Abstract: CY7C136 CY7C146
Contextual Info: CY7C132/7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The CY7C132/7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports

CY7C1362A

Abstract: GVT71512D18
Contextual Info: 7C1360A/GVT71256D36 7C1362A/GVT71512D18 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz

ATPA

Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C

CY7C136-55NI

Abstract: cy7c136 CY7C132 CY7C142 CY7C146 CY7C146-15NC CY7C136-25JXC CY7C136-55NC
Contextual Info: CY7C132, 7C136 7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 2K x 8 organization ■ 0.65 micron CMOS for optimum speed and power

Z1213

Abstract: CY7C132 CY7C136 CY7C146 zl12
Contextual Info: bSE » CYPRESS SEMICONDUCTOR SSÖ'lbbE 0 0 0 ^ 7 4 7 ISb I CYP CY7C132/7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM output enable OE . BUSY flags are pro­ vided on each port. In addition, an interrupt Functional Description Features

CY7C136

Abstract: CY7C132 CY7C146 2Kx8 Dual-Port Static RAM z1013 CY7C132-55PI CY7C136-55NC
Contextual Info: fax id: 5201 C Y 7 C 1 3 2 /C Y 7 C 1 3 6 C Y 7 C 1 4 2 /C Y 7 C 1 4 6 2Kx8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow sim ulta­ neous reads of the sam e memory location • 2K x 8 organization • 0.65-micron CMOS fo r optimum speed/power

GVT71256B36TA-7

Abstract: GVT71256B36T-7 CY7C1361A-100AI
Contextual Info: 361A 7C1361A/GVT71256B36 7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Flowthrough Burst SRAM Features • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip

b1l3

Abstract: CV7C136 CY7C1361V25 CY7C1363V25 CY7C1365V25 7C1361-133
Contextual Info: ^ _ 5r^ C Y P R F .S S 7C1361V25 7C1363V25 7C1365V25 PBEUm m m 256K x36/256K x 32/512K x 18 Flowthrough SRAM Features • Supports 113-MHz bus operations • 256K x 36 / 256K x 32/512K x 18 common I/O » Fast clock-to-output times — 7.5 ns lor 117-MHz device

Contextual Info: 7C1360A/GVT71256D36 7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

C-136B

Contextual Info: CY7C132/7C136 CY7C142/CY7C146 CYPRESS 2K x 8 Dual-Port Static RAM F ea tu res F u n ctio n al D escrip tio n • 0 .8 -m icro n C M O S for optim u m speed/ pow er • A u to m atic power-down • T T L com p atib le • C ap ab le o f w ith stan d in g g re a te r th an

30l3l

Contextual Info: CY7C132/7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR F eatures F unctional D escription • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable of withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation

81c78

Abstract: 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference
Contextual Info: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35C 2148-35M 2148-45C 2148-45C 2148-45M 2148-45M+ 2148-55C 2148-55C 2148-55M 2149-35C 2149-35C 2149-35M 2149-45C 2149-45M 2149-45M 2149-55C 2149-55C 2149-55M

CY7C136-55NI

Abstract: CY7C146 idt7132 CY7C132 CY7C136 PC TO IDT7132 CY7C136-55NC
Contextual Info: CY7C132/7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns

CY7C1361V25

Abstract: CY7C1363V25 CY7C1365V25
Contextual Info: 329 7C1361V25 7C1363V25 7C1365V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Flowthrough SRAM Features • Supports 113-MHz bus operations • 256K x 36 / 256K x 32 / 512K x 18 common I/O • Fast clock-to-output times — 7.5 ns for 117-MHz device

CY7C136E

Abstract: CY7C131AE-15JXI CY7C136AE-55NXI
Contextual Info: CY7C131E, CY7C131AE 7C136E, 7C136AE 1 K / 2 K x 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization

CY7C1367A

Abstract: GVT71512C18 4947a
Contextual Info: 7C1366A/GVT71256C36 7C1367A/GVT71512C18 256K x 36/512K x 18 Synchronous Pipelined SRAM Features 18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a

HA 13645

Contextual Info: fax id: 5201 CY7C132/7C136 CY7C142/CY7C146 2Kx8 Dual-Port Static RAM Featu res Functional Description • True Dual-Ported memory cells which allow sim ulta­ neous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power

C13220

Abstract: C1328 C1327 CY7C132 CY7C136 CY7C146 C1323 CY7C136-55NC
Contextual Info: CY7C132/7C136 CY7C142/CY7C146 2K x 8 DualĆPort Static RAM output enable OE . BUSY flags are proĆ vided on each port. In addition, an interĆ rupt flag (INT) is provided on each port of the 52Ćpin LCC and PLCC versions. BUSY signals that the port is trying to access the

Contextual Info: 1CY7C1329 7C1360A/GVT71256D36 7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining