CY7C1360 Search Results

CY7C1360C-250BGC

Abstract: CY7C1360C CY7C1362C CY7C1360C-166BZI
Contextual Info: CY7C1360C CY7C1362C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz

CY7C1362A

Abstract: GVT71512D18
Contextual Info: CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz

CY7C136B

Contextual Info: CY7C1360B CY7C1362B PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.

CY7C1360C-166BZI

Abstract: CY7C1360C166BZI
Contextual Info: CY7C1360C CY7C1362C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz

Contextual Info: CY7C1360B CY7C1362B 9-Mb 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 225 MHz • Available speed grades are 225, 200 and 166 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply

Contextual Info: CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

CY7C1360

Abstract: CY7C1360V25 CY7C1362V25 CY7C1364V25 intel 80.82
Contextual Info: CY7C1360V25 CY7C1362V25 CY7C1364V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device

CY7C1360C

Abstract: CY7C1362C
Contextual Info: CY7C1360C CY7C1362C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz Registered inputs and outputs for pipelined operation

CY7C1360B

Abstract: CY7C1362B
Contextual Info: CY7C1360B CY7C1362B 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 225 MHz • Available speed grades are 225, 200 and 166 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply

Contextual Info: 1CY7C1329 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

Contextual Info: CY7C1360C, CY7C1362C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Functional Description Features • Supports bus operation up to 200 MHz ■ Available speed grades: 200 MHz, and 166 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1360C, CY7C1362C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades: 200 MHz, and 166 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1360C, CY7C1362C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades: 250, 200, and 166 MHz ■ Registered inputs and outputs for pipelined operation

CY7C1360C

Abstract: CY7C1362C
Contextual Info: CY7C1360C, CY7C1362C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Features Functional Description n Supports bus operation up to 250 MHz n Available speed grades: 250, 200, and 166 MHz n Registered inputs and outputs for pipelined operation

CY7C1360C

Abstract: CY7C1362C
Contextual Info: CY7C1360C CY7C1362C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1360C, CY7C1362C 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades: 200, and 166 MHz ■ Registered inputs and outputs for pipelined operation

CY7C1360C

Abstract: CY7C1362C
Contextual Info: CY7C1360C CY7C1362C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz Registered inputs and outputs for pipelined operation

intel 80.82

Abstract: CY7C1360
Contextual Info: CY7C1360V25 CY7C1362V25 PRELIMINARY 256K x 36 / 512K x 18 Synchronous Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device

CY7C1360A1-150AC

Abstract: CY7C1362A1 GVT71512DA18
Contextual Info: CY7C1360A1/GVT71256DA36 CY7C1362A1/GVT71512DA18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM eral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

CY7C1360

Abstract: CY7C1360V25 CY7C1362V25
Contextual Info: V CYPRESS CY7C1360V25 CY7C1362V25 PRELIMINARY 256K x36/512K x 18Synchronous Pipelined SRAM Features • Supports 200-M Hz bus • Fully registered inputs and outputs for pipelined oper­ ation All synchronous inputs pass through input registers controlled

GVT71256D36B-5

Abstract: CY7C1362A GVT71512D18 7c136
Contextual Info: 1CY7C1329 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

CY7C1360V25

Abstract: CY7C1362V25 CY7C1364V25
Contextual Info: 329 CY7C1360V25 CY7C1362V25 CY7C1364V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device

CY7C1360A

Abstract: CY7C1362A 1362A
Contextual Info: CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns

CY7C1360A

Abstract: CY7C1362A
Contextual Info: CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns