7C256 Search Results

7C1024

Contextual Info: 6 4 K x 8 Fast S R A M ^ A S 7C 5I2 F eatures Logic B lock D iagram ♦ High Performance CMOS: tAA=12-35 ns ♦ Fast OE access: tOF=3-8 ns ♦ Low power - 688 mW 100 MHz - 27.5 mW @ 10 MHz standby - 4.25 mW @ 10 MHz standby: L version ♦ Socket compatible with 7C256,7C1024

AS7C512-20JC

Abstract: AS7C512-15PC VLN 2003 7C256 AS7C512
Contextual Info: AS7C512 5V 64K x8 CMOS SRAM 1Equal access and cycle tim es 1Easy m em ory expansion w ith CE1, CE2, OE inputs 1TTL-compatible, three-state I/O - 3 2-pin JEDEC standard packages - 300 m il PDIP and SOJ Socket com patible w ith 7C256 and 7C1024 1ESD p rotection > 2000 volts

Contextual Info: MITSUBISHI LSIs M5M2 7C256K, -2, -3 2 6 2 1 4 4 - B IT 3 2 7 6 8 - W ORD BY 8 -B IT CMOS ERASABLE AND ELECTRICALLY REPROGRAMMABLE ROM DESCRIPTION PIN CONFIGURATION (TOP VIEW) The Mitsubishi M 5 M 2 7 C 2 5 6 K is a high-speed 2 6 2 1 4 4 -b it ultraviolet erasable and electrically reprogrammable read

TAA103

Contextual Info: A 3 2 K x 8 Fast S R A M Features Logic Block Diagram ♦ High Performance CMOS: tAA=10-35 ns ♦ Fast OE access: t0 E=3-8 ns ♦ Low power - 660 m W @ 100 MHz - 11 mW @ 10 MHz standby - 2.75 mW @ 10 MHz standby: L version ♦ Automatic CE power down ♦ 2V data retention L version

intel 29F

Abstract: T7164 28F Intel LV6416 4c4007 5B810 32kxS 62832 dram cross reference T5C2568
Contextual Info: A Fast SRAM cross reference Vendor Cypress Hitachi Code ASCCode Description Code ASC Code CY 7C 185 A S7C 164 81x8 M C M 6264C AS7C164 8Kx8 CY 7C 199 A 57C 256 32K x8 M C M 6206D A S7C2S6 32K x8 C Y 7 C J3 9 9 A S7C 32S6 3 2 K * 8 3V M CM 62V06D A S7C 3256

Contextual Info: High Performance 128Kx8 C M O S SRAM p i AS7C1024 AS7C1024L 128Kx8 CM O S S RAM Common I/O FEATURES • Organization: 131,072 words x 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE1, CE2, OE inputs - 10/12/15/20/25/35 ns address access time

Contextual Info: High Performance 32Kx8 CMOS SRAM p i 7C256 7C256L 32Kx8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words x 8 bits Equal access and cycle times • High speed Easy memory expansion with CE and OE inputs - 10/12/15/20/25/35 ns address access time

7C1024

Abstract: AS7C256
Contextual Info: 7C256 5V 32K •8 CMOS SRAAA /Common I OV Features • O rganization: 3 2 ,7 6 8 w ords X 8 bits • H igh speed - 1 0 /1 2 /1 5 / 2 0 ns address access tim e - 3 / 3 / 4 / 5 ns o utput enable access tim e • Low pow er consum ption - Active: 660 m W m ax 10 ns cycle

Contextual Info: MICROCHIP TECHNOLOGY INC ESE D blü3201 0DG47Ô1 4 • <3.-251 7C256 Microchip 256K 32K x 8 CMOS UV Erasable PROM FEATURES DESCRIPTION • High speed performance —150ns maximum access time. • CMOS Technoiogy for low power consumption —20mA Active current

Contextual Info: H ig h P e r f o r m a n c e 32KX8 C M O S SR A M H A S7C 256 A 32K X 8 CMOS SRAM C om m on I / O Features • Organization: 32,768 words x 8 bits • High speed - 1 0 /1 2 /1 S /2 0 ns address access time - 3/ 3 / 4 / S ns output enable access time • Low power consumption

AS7C512-20JC

Abstract: AS7C512-15pc AS7C512 10n12 AS7C512-12JC 7C256 AS7C512L AS7CS12 Static Random Access Memory SRAM 7CS12-20
Contextual Info: High-Performance p i AS7C512 : AS7C512L CMOS SRAM 64Kx8 CMOS SRAM Common I/O FEATURES Organization; 65,536 words x 8 bits Equal access and cycle times High speed Easy memory expansion with CE1, CE2, OE inputs - 12/15/20/25/35 ns address access time TTL-compatible, three-state I/O

Contextual Info: MITSUBISHI LSIs 7C256AK-I 2 6 2 144 -B IT 3 27 68 -W O R D BY 8-B IT CMOS ER A SA B LE AND E LE C T R IC A LLY REPROGRAM MABLE ROM DESCRIPTION The M itsubishi M 5 M 2 7 C 2 5 6 A K -I is a high-speed 2 6 2 1 4 4 -b it ultraviolet erasable and electrically reprogram m able read

Contextual Info: High Performance A S7C 256L A S7C 256LL X 32K X 8 C M O S SRA M Low pow er 3 2 K x 8 CMOS SRAM Advance information Features • H ig h sp eed • 2 8 -p in JEDEC standard packages - 600 m il PDIP - 5 5 / 7 0 n s address access tim e - 3 0 / 3 5 n s o u tp u t enable access tim e

AS7C256

Contextual Info: II 81 High Performance 32Kx8 CMOS SRAM 7C256 7C256L 32Kx8 CMOS SRAM Common HO \ F E A T U R E S _ • Organization: 32,768 words x 8 bits • Completely static memory. No clocks or timing strobe required. • Equal access and cycle times

AS7C256

Abstract: 256x128x8 TI 344C
Contextual Info: High Performance 32Kx8 CMOS SRAM II ^ L lh . 7C256 7C256L 32Kx8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words x 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE and OE inputs - 10/12/15/20/25/35 ns address access time

Contextual Info: CMOS UV ERASABLE 262144-BIT READ ONLY MEMORY FU JITSU 7C256A-15 7C256A-17 7C256A-20 7C256A-25 S ep tem ber 1987 E d itio n 2.0 CMOS 262144 BIT UV ERASABLE AND ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY The Fujitsu MBM 27C 256A is a high speed 262,144 bits com plem entary MOS

C2565

Abstract: eprom mtbf CERAMIC LEADLESS CHIP CARRIER CLCC 28 7C256 CY7C256 CLCC 64 pins footprint
Contextual Info: mm ^ Yp p p c;q y SEMICONDUCTOR Features 7C256 PR ELIM IN AR Y =—" ' " - 32K x 8 PROM Power Switched and Reprogrammable • Capable o f w ithstanding > 2001V static discharge • CMOS for optimum speed/power • Windowed for reprogrammability Functional Description

Contextual Info: • bcîMTûSS 0022^50 4 fl□ ■ M I T I MITSUBISHI LSIs 7C256AK-85, -10 2 6 2 1 4 4 -B IT 3 2 7 6 8 - WORD BY 8 -B IT CMOS ERASABLE AND ELECTRICALLY REPROGRAMMABLE ROM 2 6 2 1 4 4 -b it ultraviolet erasable and electrically reprogram­ mable read only memory. It is suitable for microprocessor

AS7C256-15PC

Abstract: TSOP 8x14 AS7C256-20JC AS7C256-20PC 32KX8 7C256-15 8X13 AS7C256-10JC AS7C256-12PC 7C512
Contextual Info: H ig h P e r fo r m a n c e 32K X 8 C M O S SR A M _ I I A S 7 C 2 56 3 2 K x 8 C M O S SR A M C o m m o n I / O Features • O r g a n iz a tio n : 3 2 ,7 6 8 w o r d s x 8 b its • H ig h s p e e d • T T L -c o m p a tib le , th re e-sta te I / O

C2565

Abstract: CY7C256-55LMB C2563 CY7C256 7C256 C2564
Contextual Info: mm ^Ypppc;q y SEMICONDUCTOR Features 7C256 PR ELIM IN AR Y =— " ' " - 32K x 8 PROM Power Switched and Reprogrammable • Capable o f w ithstanding > 2001V static discharge • CMOS for optimum speed/power • Windowed for reprogrammability Functional Description

AS7C256-20JC

Abstract: AS7C256-15PC AS7C256-12JC AS7C3256-12JC AS7C3256-20JC AS7C256 AS7C256-12 AS7C256-12PC AS7C256-15 AS7C256-20
Contextual Info: 129 0%(5#4<<<# $6:&589 $6:&6589 8926169#65.ð;#&026#65$0#+&RPPRQ#,22, HDWXUHV • Very low power consumption: STANDBY - 22 mW (7C256) / max CMOS I/O - 7.2 mW (AS7C3256) / max CMOS I/O • 2.0V data retention • Easy memory expansion with CE and OE inputs

Contextual Info: AS7C512 5V 6 4K x8 C M O S SRAM Features • O rganization: 6 5 ,5 3 6 w ords X 8 bits • H igh speed - 1 5 /2 0 /2 5 ns address access tim e - 4 / 5 / 6 ns o utput enable access tim e • Low po w er consum ption - Active: 632 m W m ax 15 ns cycle - Standby: 27.5 m W max, CMOS I/O

AS7C256

Abstract: AS7C256L
Contextual Info: II II High Performance 32Kx8 CMOS SRAM 7C256 7C256L 32Kx8 CMOS SRAM Common I/O \ F E A T U R E S _ • Organization: 32,768 words x 8 bits • Completely static memory. No clocks or timing strobe required. •

AS7C256-20JC

Abstract: AS7C256 taa 723 7C256-10 7C256-12 7C256-15 AS7C256L AS7C256-15PC 7C1024
Contextual Info: High Performance 32Kx8 CMOS SRAM 7C256 7C256L 32K×8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words × 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE and OE inputs – 10/12/15/20/25/35 ns address access time