74LS22 Search Results

DN74LS22

Contextual Info: 74LS22 LS T TL DN74LS Series 74LS22 Dual 4 - input P o sitiv e NAND G ates with Open C ollector Outputs P-1 • Description DN 74LS22 contains tw o 4-input positive isolation NAND gate circuits w ith open collector outputs. ■ Features • • • •

74LS221

Contextual Info: GD54/74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT—TRIGGER INPUTS Feature • • • Pin Out is identical to the L S 12 3 B input has hysterisis for improved noise immunity Overriding Reset terminates outpulse Description Pin Configuration 1 1 HRRRRRRF1

74LS22P

Contextual Info: MITSUBISHI LSTTLs 74LS22P DUAL 4 -IN P U T P O S IT IV E NAND GATE W IT H OPEN COLLECTOR OUTPUT DESCRIPTION The M 74LS22P c o n ta in in g tw o PIN CONFIGURATION TOP VIEW is a s em ico n d u c to r 4 -in p u t po sitive-logic in teg rated NAND c irc u it

74LS22PC

Abstract: 74LS22P 74S22PC 7422PC 74H22DC 74H22PC 74LS22D 7422 74LS22DC 74H22
Contextual Info: 22 C O N N E C T IO N D IA G R A M S P IN O U T A 54/7422 ¿5//¿^ 54H/74H22 > ^4 8 /7 4 8 2 2 o / ô5 Z V54LS/74LS22 ? D U A L 4 -IN P U T N A N D G A T E W ith O p e n -C o lle c to r O utput H O R D E R IN G C O D E : See S e ctio n 9 PIN PKGS OUT C O M M E R C IA L G R A D E

20-PIN

Abstract: M74LS22P
Contextual Info: MITSUBISHI LSTTLs 74LS22P DUAL 4 -IN P U T P O S IT IV E NAND GATE W IT H OPEN COLLECTOR OUTPUT DESCRIPTION The M 74LS22P c o n ta in in g tw o PIN CONFIGURATION TOP VIEW is a s em ico n d u c to r 4 -in p u t po sitive-logic in teg rated NAND c irc u it

IC 7422

Abstract: IC 7422 g 74H22
Contextual Info: 22 CO NNECTIO N DIAGRAMS PINOUT A 54/7422 6 / ' ô < / 54H/74H22 > w/ o4S/74S22 o / ¿ 5 v54LS/74LS22 ,v/j> <r DUAL 4-INPUT NAND GATE With O pen-Collector Output ORDERING CODE: See Section 9 COMM ERCIAL GRADE PIN PKGS Vcc = +5.0 V ±5%, = 0 °C to +70° C

Contextual Info: 74LS22 LS T TL DN74LS Series 74LS22 Dual 4 - input P o sitiv e NAND G ates with Open C ollector Outputs P-1 • Description DN 74LS22 contains tw o 4-input positive isolation NAND gate circuits w ith open collector outputs. ■ Features • • • •

751A-02

Abstract: 74LS22
Contextual Info: SN54/74LS22 DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE VCC 14 LOW POWER SCHOTTKY 13 12 11 10 9 8 * * 1 2 3 4 5 6 J SUFFIX CERAMIC CASE 632-08 7 14 GND * OPEN 1 COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

74LS22

Contextual Info: & MOTOROLA SN54/74LS22 VCC [m] ni] rü] [Tn N r»i r«~i DUAL 4-INPUT NAND GATE T T Q J ' ü J I i J LU LH L lJ LOW POW ER SCHO TTKY •O PEN COLLECTOR OUTPUTS J Suffix — Case 632*08 (Ceramic N Suffix — Case 646-06 (Plastic) GUARANTEED OPERATING RANGES

DM74LS221N

Abstract: 74LS221 P 74LS221 DM74LS221M J16A LS123 M16A N16A b409 74ls221 pin diagram
Contextual Info: DM54LS221/74LS221 National Semiconductor Corporation DM54LS221/74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs General Description The DM54/74LS221 is a dual monostable multivibrator with Schmitt-trigger input. Each device has three inputs permit­

74LS22

Abstract: truth table NAND gate 74 751A-02
Contextual Info: SN54/74LS22 DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE VCC 14 LOW POWER SCHOTTKY 13 12 11 10 9 8 * * 1 2 3 4 5 6 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 * OPEN COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

SN54LSXXJ

Abstract: SN74LSXXN SN74LSXXD truth table NAND gate 74 751A-02 74LS22
Contextual Info: M MOTOROLA SN54/74LS22 DUAL 4-INPUT NAND GATE DUAL 4-IN P U T N AND GATE FÏÏ1 R nn m M m M Vcc 111 LU L il 111 LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 LU LkJ ' C E r QND ‘ OPEN COLLECTOR OUTPUTS .I’ f P T f .2 5 5 , D SUFFIX SOIC CASE 751A-02

74LS

Abstract: N74H22F N74H22N N74LS22F N74LS22N N74S22F N74S22N S54H22F S54S22F 74LS family
Contextual Info: PIN CONFIGURATIO NS 54H/74H22 54S/74S22 54LS/74LS22 ORDERING CODE See Section 9 for further Package and Ordering Information. C O M M E R C IA L RANGES ± 5%; T A = 0°C to *70°C PIN CO N F. VCC = 5V P lastic DIP Fig. A Fig. A N74S22N N74H22N . 74LS22N

LS123

Abstract: AN-372 CERAMIC DISK CAPACITOR LS221 DM74LS221 DM74LS221M DM74LS221N M16A N16A AN-372 fairchild
Contextual Info: S E M IC O N D U C T O R tm 74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs General Description The DM 74LS221 is a dual m onostable m ultivibrator with S chm itt-trigger input. Each device has three inputs perm it­ ting the choice of either leading-edge or trailing-edge trig ge r­

74LS221

Abstract: 74LS221 P TTL 74ls221 PM211 54LS221
Contextual Info: DESCRIPTION PIN CONFIGURATION The S4/74LS221 Is a monolithic dual multivibrator which features a negative-transitiontriggered input either of which can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse.

74LS221P

Abstract: Capacitor 47nS
Contextual Info: MITSUBISHI LSTTLs M 74LS221P DUAL M ONOSTABLE MULTIVIBRATOR DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74 LS 2 21 P is a sem iconductor integrated circuit containing tw o monostable m ultivibrator circuits w ith direct reset inputs. 1A TRIGGER INPUTS FEATURES

IC 7412

Abstract: IC 7420 IC 7422 74LS22 282A 7420 ic
Contextual Info: -3 6 Dual 4 Input 0. C. NAND 7422 Vçç 2D 2C NC 28 2A 2V TJTTiimnïmnir 1A o 7420<D t - 1B NC 1C 7" > TJ U 7 9 9 ID i y1 74LS22 IV GNO

LS224

Abstract: LS222 WL 431 16X4 SN74LS228 sn74*222 1LS224 LS228
Contextual Info: SN54LS222, SN54LS224. SN 54LS227, SN54LS228 74LS222, 74LS224, SN 74LS227, 74LS228 1 6 X 4 SYNCHRONOUS FIRST IN FIRST OUT MEMORIES JA N U A R Y 1981 R E V IS E D M A R C H 1 9 8 5 S N 5 4 L S 2 2 2 , S N 5 4 L S 2 2 7 . . . J PAC KA G E S N 7 4 L S 2 2 2 , S N 7 4 L S 2 2 7 . . . J OR N PAC KAG E

Contextual Info: SN5422, SN54LS22, SN54S22, SN7422, 74LS22, SN74S22 DUAL 4-INPUT POSITIVE-NANO GATES WITH OPEN-COLLECTOR OUTPUTS DE C EM B ER 1 9 83 - R E V ISE D M A R C H 1988 SN 5422, SN 54LS22. SN 5 4 S2 2 . . . J OR W PACKAG E SN 7422 . . . N PACKAGE SN 74LS22. S N 7 4 S 2 2 . . . D O R N PACKAG E

IC 7422

Abstract: 7422 74LS22D as 5422 T3228
Contextual Info: SN5422, SN 54LS22, SN54S22, S N 7422 , S N 74 LS 2 2 , SN 74S22 D U A L 4-INPUT POSITIVE N A N D G A TES W ITH O P EN C O LLEC TO R O U TPU TS DECEMBER 1983 - REVISED MARCH 19B8 Package Options Include Plastic "Small Outline” Packages, Ceramic Chip Carriers

Contextual Info: /TC74HC221AP/AF/AFN D U A L MO NO STABLE M U L T I V I B R A T O R T he TC74HC221A is a hig h speed CM OS MONOSTABLE M U L T IV IB R A T O R fa b ric ate d w ith silico n g a te C 2MOS tech no lo g y. It achieves th e high speed o p e ratio n s im ila r to eq u iv alen t

Contextual Info: TC74HC221AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC221AFN Dual Monostable Multivibrator Note: xxxFN JEDEC SOP is not available in Japan. The TC74HC221A is a high speed CMOS MONOSTABLE TC74HC221AFN MULTIVIBRATOR fabricated with silicon gate C2MOS

TC74HC221AF

Abstract: 74LS221 TC74HC221AP RX-2 -G s 174 PF 74LS221 IC
Contextual Info: TC74HC221AP/AF 東芝CMOSデジタル集積回路 シリコン モノリシック TC74HC221AP,TC74HC221AF Dual Monostable Multivibrator TC74HC221A は ､ シ リ コ ン ゲ ー ト CMOS 技 術 を 用 い た 高 速 CMOS 2 回路入りモノステーブル•マルチバイブレータです。

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES