74LS19 Search Results

DN74LS194A

Abstract: MA161
Contextual Info: ! LS TTL DN74LS Series 74LS194A 74LS194A 4 -b it Bidirectional Universal Shift R egisters • Description P-2 DN 74LS194A is a bidirectional 4-bit serial/parallel input to serial/parallel output shift register. ■ • • • • • • Features Synchronous serial/parallel input to serial/parallel output

Contextual Info: Am25LS194A • Am54LS/74LS194A Am25LS195A • Am54LS/74LS195A Four-Bit High-Speed Shift Registers D IS TIN C TIV E C H AR A C TE R IS TIC S • • • • • LOGIC D IA G R A M S S hift righ t or parallel load w ith JK inputs on A m 25LS 195A S hift le ft, right, parallel load or do nothing on A m 25LS 194A

74LS190 up down decade counter

Abstract: 74LS190 PIN diagram 74LS190 pins 74LS190 ad 440J 74LS190 APPLICATIONS function 74ls190 74LS190 application
Contextual Info: Am25LS190 • Am54LS/74LS190 Am25LS191 • Am54LS/74LS191 Synchronous Counters With Up/Down Mode Control LO G IC D IA G R A M S D IS T IN C T IV E C H A R A C T E R IS T IC S • • • Single u p /d o w n c o u n tlin e Parallel load in p u ts and parallel c o u n t o u tp u ts

BCD 8421

Abstract: pin diagram decade counter 74196 pin diagram of 74196 BCD counter circuit diagram max plus binary to BCD 8421 74196 74196PC 74LS196PC 54196FM 54LS196DM
Contextual Info: 196 C O N N E C T IO N D IA G R A M P IN O U T A o/oo3^ \À ¡4/74196 a 54LS/74LS196 £>/ 0 o 3& PRESETTABLE DECADE COUNTERS D E S C R IP T IO N — T he '196 d e ca de rip p le co u n te r is p a rtitio n e d in to d iv id e b y -tw o and d iv id e -b y -fiv e s e ctio n s w h ich can be c o m b in e d to c o u n t e ith e r in

Contextual Info: GD54/74LS195A 4-BIT PARALLEL ACCESS SHIFT REGISTERS Features • • • • • • • Synchronous parallel load Positive-edge-triggered clocking Parallel inputs and outputs from each flip-flop Direct overriding clear J and K inputs to first stage Complementary outputs from last stage

ci 74190

Abstract: 4LS192 ic 74190 L5192 ci 74192 T74192 74192 74192 ic ic 74192 CT54190
Contextual Info: CT54190/CT74190 C T 54 L SI 90 /C T 74 L S 190 C T R D IV 10 190 M l l t t + i & M H ÿ t o / t t t t - f t t t , * # 54/741 90 W 54/74LS190 4 , S fc C T 54190/CT74190 25MHz 325mW CT 54 L S 19 0 /CT74 L S 190 25MHz lOOmW 190 fftttM t tA W b i a s i m i < ld ) â « i w

74LS193 function table

Contextual Info: GD54/74LS193 SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS.BINARY WITH CLEAR Feature Pin Configuration • Cascading Circuitry Provided Internally • Synchronous Operation • Individual Preset to Each Flip-Flop • Fully Independent Clear Input INPUTS INPUTS Vcc

74191 8 bit

Abstract: 7443 Flip-Flop D134 7443 d Flip-Flop 74LS42 74155 9B23 D135 93L38 93L11
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

74LS190 PIN diagram

Abstract: ttl 7442 74LS42 74LS138 pin diagram D134 7442 pin diagram 74155 74145 D133 93L01
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

7448 decoder

Abstract: ID 9302 Fairchild 74190 pin diagram decoder 7447 TTL 7448 74LS47 74LS47 pin TTL 7446 decoder 74LS47 decoder 7448
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 G N D = Pin 8 Vcc = Pin 16 G N D = Pin 8

transistor d133

Abstract: Decoder BCD 7 seg ttl 7442 transistor 6B 7-seg ANODE COMMON 74155 74LS247 pin diagram of 74LS247 ttl 74191 75491
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

TTL 74150

Abstract: 74151 TTL 7452 74151 PIN DIAGRAM 74195 logic diagram 74LS95 74LS152 74155 PIN DIAGRAM 74155 93H00
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D163 9300, 93H00, 93L00, 93S00, 54/74195, 54LS/74LS195 0162 54/74150 V cc = Pin 16 G N D = Pin 8 V cc = Pin 24 G N D = Pin 12 D164 93H72 D166 54/7495, 54LS/74LS95, 54LS/74LS95B D165 54/7494 1 16 2 14 3 13

74LS192 truth table

Abstract: 74LS193 truth table 74LS192 PIN diagram 74ls193 74LS192 74LS192 INTERNAL DIAGRAM TTL 74ls193 74LS193 pin data 74LS192 table ttl 74ls192
Contextual Info: SN54/74LS192 SN54/74LS193 PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER PRESETTABLE BCD/ DECADE UP/ DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade 8421 Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate

74LS194A

Abstract: LS195A SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS194A 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER The SN54 / 74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift

Contextual Info: <8 > M OTOROLA SN 54LS195A SN 74LS195A D E S C R IP T IO N — T he S N 5 4 L S /7 4 L S 1 9 5 A is a h ig h speed 4 - B it S h ift R e g iste r o ffe rin g ty p ic a l s h ift fre q u e n c ie s o f 3 9 M H z. It is u s e fu l fo r a w id e v a rie ty o f re g is te r a n d c o u n tin g a p p lic a tio n s . It u tiliz e s th e

LS195A

Contextual Info: M M O T O R O L A SN54/74LS195A UNIVERSAL 4-BIT SHIFT REGISTER The SN54/74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to

74LS192P

Abstract: OB2223
Contextual Info: MITSUBISHI LSTTLs M 74LS192P SYNCHRONOUS PRESETTABLE U P /D O W N DECADE COUNTER DESCRIPTION The 74LS192P is a semiconductor integrated circuit containing a synchronous decade up/down counter func­ tion with direct reset and preset inputs. PIN CONFIGURATION TOP VIEW

74LS195A

Abstract: LS195A SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS195A UNIVERSAL 4-BIT SHIFT REGISTER The SN54 / 74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to

74193PC

Abstract: 74ls193p 74LS193PC ic 74193
Contextual Info: I ' NATI ONAL S E HI C OND {LOGIC} D5E D | bSG112E DOLLES E | 7 ^ ^ 5 -2 3 -0 7 193 CO NN ECTIO N DIAGRAM PINO UT A 54/74193 54LS/74LS193 1 Ü ] Vcc UP/DOWN BINARY COUNTER With Separate Up/down Clocks D E S C R IP T IO N — The '193 is an up/dow n m odulo-16 binary counter. Sep­

Contextual Info: - ì NATIONAL SEflICOND { L O G I C * OSE D | ¿,501125 0 0 ^ 3 7 T | _ - T - V 5 - ^ 3 -l3 _ 1 9 7 CO NNECTIO N DIAGRAM PINOUT A 54/74197 54LS/74LS197 [7 ch T 7T| V cc PL PRESETTABLE BINARY COUNTERS 13] MR P2 | T DESCRIPTION — The '197 rippie counter contains divide-by-tw o and divideby-e igh t sections w h ich can be com bined to form a m odulo-16 binary

74LS192 PIN CONFIGURATION

Contextual Info: LS TTL DN74LS Series 74LS192 74LS192 lv>7^ i£ R % Synchronous BCD Up / Down Dual Clock Counters with Reset • Description P-2 D N 74LS192 is a synchronous decade u p/dow n counter w ith direct-coupled reset in p u t and set input. ■ • • • •

M74LS196P

Abstract: T280 20-PIN
Contextual Info: MITSUBISHI LSTTLs M 74LS196P P R E S E T T A B L E DECADE COUNTER/LATCH DESCRIPTION The M 7 4 LS 1 9 6 P PIN CONFIGURATION TOP VIEW is a sem iconductor integrated circuit containing an asynchronous decade counter function with direct reset input and preset input.

pht 094

Abstract: 400M DN74LS196 MA161
Contextual Info: LS TTL DN74LS Series D N 7 4 L S 1 9 DN74LS3 96 6 30M H z S ettable Decade Counters / L atches I D e s c rip tio n D N 74LS196 is an asynchronous decade counter with directcoupled reset input and set input. P-1 • Features • Direct-coupled reset input and asynchronous set input

DN74LS197

Abstract: MA161
Contextual Info: LS TTL DN74LS Series D N 7 4 L S 1 9 7 k DN74J.S197 > 74-L £ì^ 7 30M H z Settab le Binary Counters / L atches • Description P-1 D N 74LS197 is an asynchronous hexadecim al 4-bit binary cou n ter w ith direct-coupled reset in p u t and set input. H Features