74LS GATES Search Results

octal Bilateral Switches

Abstract: MM74HC14M MM74HC138M CD4025BCM MM74HC00M MM74HC74AM MM74HC125M MM74HC04M cd4046bcm cd4052bcm
Contextual Info: 1/3 CMOS LOGIC MM74HC SERIES MM74HCT/U SERIES • HIGH SPEED CMOS TECHNOLOGY, CMOS DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES Part Number Description • HIGH SPEED CMOS TECHNOLOGY, TTL DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES SQP £ ea. Gates & Inverters

lm294oct

Abstract: d71054c D71055C lm294oct-12 74c928 7486 XOR GATE interfacing ADC 0808 with 8086 microprocessor 555 7490 7447 7 segment LED display Motorola 74LS76 NEC D71055C
Contextual Info: Integrated Circuits 74LS Series Featuring better performance than standard 7400 series devices, the 74LS series also uses about 1/5th the power. Part# Pins Description 74LS00 74LS01 74LS02 74LS03 74LS04 74LS05 74LS06 74LS07 74LS08 74LS09 74LS10 74LS11 74LS12

74LS18P

Contextual Info: MITSUBISHI LSTTLs M 74LS 18P DUAL 4-IN P U T NAND SCHMITT TRIGGER DESCRIPTION The M 74LS 18P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing tw o 4-input positive-logic N A N D gates having a schm itt trigger function and negative-logic N O R gates.

74L86

Contextual Info: SN54LS386A, SN74LS386A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES MARCH 1974 - REVISED MARCH 198B SN 54LS 386A . . . J OR W PACKAGE SN 74LS 386A . . . D OR N PACKAGE Electrically Identical to SN54LS86A/SN74LS86A TOP VIEW Mechanically Identical to SN 54L86/S N 74L86

74hctls

Contextual Info: Zyfrex ZX54HCTLS M M m % ZX74HCTLS Quad 2-Input NAND Gates with Open-Drain Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input NAND

Contextual Info: GD54/74HC32, GD54/74HCT32 QUAD 2-INPUT OR GATES General Description These devices are identical in pinout to the 54/74LS 32. They contain four independent 2-input OR gates. These devices are characterized for operation over wide temperature ranges to meet in­

Contextual Info: GD54/74HC86, GD54/74HCT86 QUAD 2- INPUT EXCLUSIVE OR GATES General Description These devices are identical in pinout to the 54/74LS 86. They contain four independent 2-input Exclusive OR gates. These devices are characteriz­ ed for operation over wide temperature ranges to

Contextual Info: MITSUBISHI LSTTLs M 74LS136P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATES W ITH OPEN COLLECTOR OUTPUTS DESCRIPTION The M 74LS 136P containing 4 is a semiconductor integrated circuit dual-input exclusive-OR gates w ith PIN CONFIGURATION TOP VIEW open collector output.

74HCoo

Abstract: TTL 74HC00 74LS00 pinout pin diagram of 74ls00 74HC00 GD74HC00 logic symbol 74LS00 74hc00 and gates pin configuration logic symbol 74LS00 74LS00 gate diagram
Contextual Info: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS 00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­

74hctls

Contextual Info: Zytrex_ æ&OO Quad 2-Input NAND Gates February 1965 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input NAND gatesJhat perform the Boolean functions Y = A • B or

SN74LS166

Abstract: 74LS LS166 SN74LS166D SN74LS166DR2 SN74LS166M SN74LS166MEL SN74LS166N
Contextual Info: SN74LS166 8-Bit Shift Registers The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified.

74LS166

Abstract: 74LS LS166 SN54LSXXXJ SN74LSXXXD SN74LSXXXN parallel to serial conversion
Contextual Info: SN54/74LS166 8-BIT SHIFT REGISTERS The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54 / 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and

74LS58

Abstract: 74HCT58 GD74HC58 54/74LS58 74HC GD54HC58
Contextual Info: GD54/74HC58, GD54/74HCT58 DUAL AND-OR GATES General Description These devices are identical in pinout to the 54/74LS 58. They contain one 2-wide 2-input & one 2-wide 3-input AND-OR gates. These devices are characterized for operation over wide temperature ranges to meet industry and military

IC 74LS47

Abstract: pin diagram of 74LS47 TTL IC 74ls470 motorola 74ls47 74LS47 7-segment 74ls47 74LS47 functions 74LS47 gate diagram 74LS47 pin ic 74ls47 and 7 segment
Contextual Info: g MOTOROLA SN54/74LS47 BCD TO 7-SEGMENT DECODER/DRIVER The S N 54/74LS 47 are Low Power Schottky BCD to 7-Segment Decod­ er/D rivers consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. They offer active LOW, high sink current outputs for driving

D73-Y

Abstract: D73y ic 74145
Contextual Info: SAMSUNG SEM IC O N D U C T OR INC 05 DEI 7^4145 . KS54HCTLS O O KS74HCTLS ~ 000^301 S T -4 3 -a i Quad 2-Input OR Gates FEATURES DESCRIPTION • Function, pln-out, speed and drive compatibility with 54/74LS logic family • Low power consumption characteristic of CMOS

FZH115B

Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Contextual Info: Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P

diagram for 4 bits binary multiplier circuit

Abstract: 74LS 219 74LS261 N74LS00 S54LS00 s54ls181
Contextual Info: SPEED/PACKAGE AVAILABILITY 54LS F,W PIN CONFIGURATION 74LS B B,F,W PACKAGE DESCRIPTION 83La These low-power Schottky circuits are designed to be used in parallel multiplication appli­ cations. They perform binary multiplication in two’s-complement form, two bits at a time.

M74LS10P

Abstract: mitsubishi air conditioning 20-PIN 74LS10P
Contextual Info: MITSUBISHI LSTTLs M 74LS10P T R IP L E 3 -IN P U T P O S IT IV E NAND GATES DESCRIPTION The M 74LS 10P is a semiconductor integrated circuit containing three triple-input positive N A N D and negative N O R gates. FEATURES • High breakdown input voltage V | ^ 15 V

74LS10P

Abstract: M74LS10P
Contextual Info: M IT S U B IS H I L S T T L s M 74LS10P TRIPLE 3-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 10P is a semiconductor integrated circuit containing three triple-input positive N A N D and negative N O R gates. FEATURES • High breakdown input voltage V | ^ 15 V

decade counter circuit diagram

Abstract: 25LS192 up down counter 1N3064 25LS193
Contextual Info: I 25LS192 Synchronous BCD Decade Up/Down Counter 25 LS193 Synchronous 4-Bit Binary Up/Down Counter PIN-OUT DIAGRAM FEATURES • ■ ■ ■ ■ Separate clock inputs for count-up, count-down Asynchronous parallel load and clear Cascadable Higher speed compared to 9LS/54LS and 9LS/74LS

M74LS00P

Abstract: 20-PIN M74LS00
Contextual Info: M IT S U B IS H I LSTTLs M74LS00P QUADRUPLE 2-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 00P is semiconductor integrated circuit contain­ ing fo u r dual-input positive-logic N A N D gates, usable as negative-logic N O R gates. FEATURES • High breakdown input voltage V | S 15 V

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gates 74LS series logic gate symbols 74ls gate symbols 74125 ic 74LS126 74LS55 r025 74LS125 74LS51
Contextual Info: FAIRCHILD DIGITAL TTL High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram 2 High Speed 54H/74H 6 ns/22 mW Std. TTL 9N 54/74 10 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Item 9000 Series 8 ns/10 mW (Cont'd) Function’11 SSI FUNCTIONS 5 't/I

54LS

Abstract: 74LS
Contextual Info: SWITCHING CHARACTERISTICS vCc - 5V, r A = 25°c T E S T CONDITIONS PARAMETER FROM INPUT TO OUTPUT Any MIN 54/74LS 54/74S C L =15pF R L = 2K îî C|_=15pF R|_=280ii TYP MAX MIN TYP MAX LEV ELS O F DELAY UNIT 2 ns Propagation delay time tp|_H Low-to-htgh Binary

SN54138

Abstract: SN74LS138 LS138 SN54LS138 SN54S138 SN74S138A gl 1151
Contextual Info: SN54LS138, SN54S138, SN74LS138, SN74S138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D E C E M B E R 1972 — R E V IS E D M A R C H 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems S N 54LS 138, S N 54S 138 SN 74LS 138, S N 74S 138A