D74LS Search Results

ATML U 010

Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H D74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

74LSOO

Abstract: HD74LS374 HD74LSoop
Contextual Info: D74LS374 • O c t a l D-type Edge-triggered Flip-Flops with th ree-state IP IN ARRANGEM ENT The H D74LS374, 8-bit registers features totem-pole threestate outputs designed specifically for driving highly-capacitive or relatively iow-impedance loads. The high-impedance third

D74LS175

Abstract: 74LS174 example S174H HD74LSoop 74ls175
Contextual Info: H D 74LS174/H D74LS175 •H e x Quadrupte D-type Rip-Hops with clear IBLOCK DIAGRAM These positive-edge-triggered flip-flops utilize T T L circuitry to implement D-type flip-flop logic. A ll have a direct clear input, and the H D74LS175 features complementary outputs

HD74LSoop

Contextual Info: I I I n U C O / ^ r L O O T O / O • O c t a l D-type Transparent Latches with th ree-state outputs (PIN ARRANGEM ENT The H D74LS373, 8-bit register features totem-pole three-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance third

D74LS

Abstract: BCD-to-seven-Segment Decoders 74LSO
Contextual Info: • BCD-to-Seven-Segment Decoders/Drivers with open collector outputs The H D 74LS249 is 16-pin versions of the D74LS49, respec­ tively. Included in the H D74LS249 circuits is the full func­ • P IN A R R A N G E M E N T tional capability for lamp test and ripple blanking, which is

1S2074

Abstract: 74LSOO HD74LS160 Hitachi Scans-001
Contextual Info: H D74LS160 •Synchronous Decade Counters direct clear T his s y n c h r o n o u s decade counter features an internal carry look­ ahead for application in high-speed counting designs. Synchronous ope* ration is provided by having all flip-flops clocked simultaneously so

hd74ls pin

Abstract: 74LSOO HD74LS HD74LS249 HD74LS49 D74LS
Contextual Info: • BCD-to-Seven-Segment Decoders/Drivers with open collector outputs The H D 74LS249 is 16-pin versions of the D74LS49, respec­ tively. Included in the H D74LS249 circuits is the full func­ • PIN ARRANGEMENT tional capability for lamp test and ripple blanking, which is

Contextual Info: # 4 - b y - 4 Register File with open collector outputs The H D74LS170 is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits simultaneous writing into one location and reading from

74LSOO

Abstract: HD74LS49 HD74LSoop Hitachi Scans-001
Contextual Info: • BCD-tO’Seven Segment Decoder/Driver with Open collector outputs IP IN ARRANGEMENT The H D74LS49 features active-high outputs for driving lamp buffer. This circuit incorporates a direct blanking input. Segment identification and resultant displays are shown below.

HD74LS04

Abstract: HD74LS05 74LSOO Hitachi Scans-001
Contextual Info: D74LS04/H D74LS05 • H e x In ve rters with Open Collector Outputs • CIRCUIT SCHEMATICO^) «PIN ARRANGEMENT Item Symbol min typ max High level output voltage Voh - - 5 .5 Low level output c u rre n t Iol - - 8 Unit V mA ■ ELECTRICA L CH A RA CTERISTICS ( Ta= -20~ + 75’C )

HD74LSoop

Abstract: 1S2074 74LSOO HD74LS195A Hitachi Scans-001 Scans-0014928
Contextual Info: H D 74 L S 19 5A . 4-b¡t Parallel-Access Shift Registers This 4-bit register features parallel inputs, parallel outputs. is loaded into the associated flip-flop and appears at the out­ puts after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished

101902

Abstract: 54LS503DMQB 54LS503FMQB DM74LS503N J16A M16B VCC71
Contextual Info: LS503 CT1 National Juâ Semiconductor 54LS503/DM74LS503 8-Bit Successive Approximation Register with Expansion Control General Description Features The 'LS503 register is basically the same as the ’LS502 except that it has an active LOW Enable (E) input that is

1S2074

Abstract: 74LSOO HD74LS273
Contextual Info: u n n i i i i C O T O U / T L w f a / w t o c ta l D -typ e P o s itiv e -e d g e -trig g e re d F lip -F lo p s w ith Clear The D74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a direct clear input

saat

Abstract: bcd counter ic number HD74LSOO
Contextual Info: • 4 - b i t Binary Counters This counter contains four master-slave flip-flops and addi­ tional gating to provide a divide-by-two counter and divide-byeight counter. This counter has a gated zero reset .To use the maximum count length of this counter, the B input is con­

IC 74LS160

Abstract: 74LS160 function of the ic D74LS
Contextual Info: H D 74 LS160 •Synchronous Decade Counters direct clear T his s y n c h r o n o u s decade counter features an internal carry look­ ahead for application in high-speed counting designs. Synchronous ope* ration is provided by having all flip-flops clocked simultaneously so

GD74LS04

Abstract: d74ls0 GD74LS257 D74LS04
Contextual Info: GD54/74LS257A QUAD DATA SELECTORS/MULTIPLEXERS; NON-INVERTED 3-STATE OUTPUTS Feature Pin Configuration • T h ree -S ta te O utputs In terface Directly with S ystem Bus • Provides Bus Interface from M ultiple S ources in H ig h-Perform ance S ystem •

74LSOO

Abstract: 1S2074 HD74LS160 vh08 Hitachi Scans-001
Contextual Info: H D 74LS 160 •Synchronous Decade Counters direct clear T his s y n c h r o n o u s decade counter features an internal carry look­ ahead for application in high-speed counting designs. Synchronous ope* ration is provided by having all flip-flops clocked simultaneously so

1S2074

Abstract: 74LSOO HD74LS293
Contextual Info: • 4 -b it Binary Counters This counter contains four master-slave flip-flops and addi­ tional gating to provide a divide-by-two counter and divide-byeight counter. Th is counter has a gated zero reset.To use the maximum count length of this counter, the B input is con­

triac tag 8518

Abstract: 70146 DS3654 X2864AD 7 segment display RL S5220 TC9160 la 4440 amplifier circuit diagram 300 watt philips ecg master replacement guide vtl 3829 A-C4 TCA965 equivalent
Contextual Info: 1985 0 / 0 / CONTENTS VOLUME I Introduction to IC MASTER 3 Advertisers’ Index 8 Master Selection Guide Function Index I0 Part Number Index 40 Part Number Guide 300 Logo Guide 346 Application Note Directory 349 Military Parts Directory 50I Testing 506 Cross Reference

74LS00 clock frequency

Abstract: 74LS00 function table pin configuration 74LS00
Contextual Info: GD54/74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates. K performs the Boolean functions Y = A B or Y = A + B in positive logic. Pin Configuration V cc 4B 4A 4Y 3B 3A 14 13 12 11 10 9 3Y 8 lIoJ lioJ

UL224D30

Abstract: UB880D radio fernsehen elektronik selen-gleichrichter L6516DG15 selengleichrichter L224D U6516dg bauelemente Kombinat D74LS999DK U6516D L6516DG15
Contextual Info: Typbezeichnung u nd K ennzeichnung von H alb le iterb a u e lem e n te n Dipl.-Ing. PETER H A N D R A C K Mitteilung aus dem V EB Kombinat Mikroelektronik Erfurt Ziel der Überarbeitung der TGL 38015 war es, sowohl die bei der A rbeit m it der beste­ henden Ausgabe gewonnenen Erfahrungen

HD74LS152

Abstract: 1S2074 74LSOO
Contextual Info: # 1 -of-8 Data Selectors/Multiplexers This data selector/multiplexer contains fuil-on-chip binary decoding to select the desired data source. The D74LS152 selects one-of-eight data sources. • B LO C K DIAGRAM flP IN ARRAN GEM EN T ■ FUNCTION T A B LE

IC 74LS283 pin diagram

Abstract: 74LSOO 1S2074 HD74LS283 HD74LS83A full adder 2 bit ic 74LSOOP
Contextual Info: • 4 - b i t Binary Full Adders • PIN A R R A N G E M E N T . . the terminals has been changed. This improved full adder performs the addition of two 4-bit w *E binary words. The sum 2 outputs are provided for each bit and the result­ ant carry (C4 ) is obtained from the fourth bit. This adder

1S2074

Abstract: 74LSOO HD74LS175
Contextual Info: D74LS174/H D 74LS175 These positive-edge-triggered flip -flo p s u tilize T T L c ircu itry • H e x Quadrupte D-type Rip-Hops with clear ¡B LO C K DIAGRAM to im plem ent D-type flip -flo p logic. A ll have a d irect clear in p ut, and the H D 7 4 L S 1 7 5 features com plem entary outputs