HD74LS Search Results

Contextual Info: HD74LS390 Dual Decade Counters REJ03D0485-0400 Rev.4.00 May 10, 2006 This circuit contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters. The HD74LS390 incorporates dual divide-by-two and divide-by-five counters, which can be used to implement cycle

Contextual Info: HD74LS165A Parallel-Load 8-bit Shift Register REJ03D0449–0300 Rev.3.00 Jul.15.2005 The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift /

DIVIDE-BY-256

Abstract: ONU block diagram 74LSOO HD74LS393 a63a
Contextual Info: •D u a l 4-bit Binary Counters This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement tw o individual four-bit counters. The HD74LS393 comprises tw o independent four-bit binary counters each having a clear and a clock input.

74LSOO

Abstract: HD74LS490
Contextual Info: HD74LS490. This c irc u it d itio n a l contains gating to eigh t master-slave im p le m e n t tw o Dual 4 -b it Decade Counters flip -flo p s ind ividu al 4 -b it and ad ­ I BLOCK DIAGRAM K decade counters. Each decade c o u n te r has ind ividu al clo ck, clear, and

74LSOO

Abstract: HD74LS367A kl66
Contextual Info: HD74LS367A * Hex Bus Drivers non-inverted data outputs with three-state outputs I PIN ARRANGEMENT I CIRCUIT SCHEMATIC D r i v e r se c tio n (1 / 6 ) C o n t r o l se c tio n Ootpu Control Ci ~ï7 ]vVcc — 1Output Cont roi Ci 'vLLKy L jc t-E I 6 " Y r]D *

74LSOO

Abstract: HD74LS374 HD74LSoop
Contextual Info: HD74LS374 • O c t a l D-type Edge-triggered Flip-Flops with th ree-state IP IN ARRANGEM ENT The H D74LS374, 8-bit registers features totem-pole threestate outputs designed specifically for driving highly-capacitive or relatively iow-impedance loads. The high-impedance third

74LSOOP

Abstract: 74LSOO
Contextual Info: HD74LS21 •D u al 4-input Positive AND Gates •PIN ARRANGEMENT ¡CIRCU IT SCHEMATICO^ ■ ELECTRICAL CH A RA CTERISTICS Item Symbol Input voltage VlL I6i IlH Input current IlL ¡1 Short-circuit output current Supply current Input clamp voltage * T est Conditions

DP 804 C

Abstract: JV3 diode 74LSOO HD74LS221
Contextual Info: HD74LS221 »Dual Monostable Multivibrators This multivibrator features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the tran­

IS2074 diode

Abstract: flip flap 1S2074 400M HD74LS78A
Contextual Info: HD74LS78A Dual J-K Flip-Flops (with Preset. Common Clear, and Common Clock IBLOCK D IA G R A M ^ ) IP IN A R R A N G E M E N T •RECOMMENDED OPERATING CONDITIONS Ite m C lock fre q u e n c y Clock High w idth t* Preset r C le ar Sym bol fr t.r k Low min

1S2074

Abstract: HD74LS76A Hitachi Scans-001
Contextual Info: HD74LS76A. Dual J -K Flip-Flops w ith Preset and Clear IBLOCK D IA G R A M (12) IP IN A R R A N G E M E N T 7T| ix CK [ T PR "L 77] to PR CLR LR >-, Q Ö Lfi UE iDr 77] io 13 I CN 'cc ( T 77] 2K CK £7 ^ 77] 2Q 10 [ 2Q PR ~9~] 2J î, e (R E C O M M E N D E D OPERATING C O N D IT IO N S

74LSOOP

Contextual Info: HD74LS02 •Quadruple 2-input Positive NOR Gates ICIR CU IT SCHEMATICO^ IPIN ARRANGEMENT • ELECTRICAL CH ARACTERISTICS T a = -2 0 ~ +75°C ) Item Symbol T est Conditions min typ* VlH 2 .0 - - V VlL _ - 0 .8 V V Input voltage VOH Vcc —4 .7 5 V, V/l = 0 . 8 V , / oh= - 4 0 0 M

Contextual Info: u n i i i i c o t o r l U / t r L O ^ / O t o c tal D -type P o s i ti v e - e d g e - tr ig g e r e d Flip-Flops with Clear The HD74LS273, positive-edge-triggered flip-flops utilize LS T T L circuitry to implement D-type flip-flo p logic w ith a direct

HD74LS47

Contextual Info: • BCD-to-Seven-Segment Decoder/Driver with 15V Outputs HD74LS47 features active-low outputs designed for driving • P IN ARRANGEMENT incandescent indicators directly. This, device has full rippleblanking input/output controls and a lamp test input. Display

Contextual Info: HD74LS243 Quadruple Bus Transceivers with three-state outputs REJ03D0462–0300 Rev.3.00 Jul.15.2005 Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS243FPEL SOP-14 pin (JEITA)

Contextual Info: HD74LS280 9-bit Odd / Even Parity Generator / Checker REJ03D0475–0300 Rev.3.00 Jul.15.2005 This parity generator / checker offers the designer a trade-off between reduced power consumption and high performance. Although the HD74LS280 is implemented without expander inputs, the corresponding function is

Contextual Info: HD74LS40 Dual 4-input Positive NAND Buffers REJ03D0408–0200 Rev.2.00 Feb.18.2005 Features • Ordering Information Part Name Package Type Package Code Previous Code Package Abbreviation Taping Abbreviation (Quantity) HD74LS40FPEL SOP-14 pin (JEITA) PRSP0014DF-B

Contextual Info: HD74LS160A Synchronous Decade Counter direct clear REJ03D0444–0300 Rev.3.00 Jul.15.2005 This synchronous decade counter features an internal carry look ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes

Contextual Info: HD74LS266 Quadruple 2-input Exclusive-NOR Gates with open collector outputs REJ03D0472–0200 Rev.2.00 Feb.18.2005 Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS266P

Contextual Info: HD74LS195A 4-bit Parallel-Access Shift Register REJ03D0457–0300 Rev.3.00 Jul.15.2005 This 4-bit register features parallel inputs, parallel outputs, J-K serial inputs, shift / load control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The registers have two modes of

IC hd74LS14p

Abstract: HD74LS14P HD74LS14RPEL HD74LS14P ic data
Contextual Info: HD74LS14 Hex Schmitt Trigger Inverters REJ03D0399-0400 Rev.4.00 Apr 07, 2009 Features • Ordering Information Part Name Package Type Package Code Previous Code Package Abbreviation Taping Abbreviation (Quantity) HD74LS14P DILP-14 pin PRDP0014AB-B (DP-14AV)

74ls series logic family

Abstract: SN74HC logic family CMOS 4000 TTL 74ALS CMOS 4000 Series family cmos logic 4000 series 74LS TTL 245 74ls TTL family 74ls series family cross reference cmos 4000
Contextual Info: INTEGRAL KOREA Cross Reference Characteristics Technology IK Semi Hitachi IN74 TTL CMOS 4000 On Semi Toshiba TI Philips Fairchild SN74 SN74 SN74 74 DM74 IN74LS HD74LS SN74LS SN74LS SN74LS 74LS DM74LS IN74ALS HD74ALS SN74ALS SN74ALS SN74ALS 74ALS DM74ALS IW4

cmos logic 4000 series

Abstract: TTL 74ALS 74 series TTL NOT gate MM74HC CMOS 4000 Series family 74ls series logic family CMOS 4000 SN74HC logic family 74ls TTL family 74ALS
Contextual Info: z Cross Reference Characteristics Technology IK Semi Hitachi IN74 TTL CMOS 4000 On Semi Toshiba TI Philips Fairchild SN74 SN74 SN74 74 DM74 IN74LS HD74LS SN74LS SN74LS SN74LS 74LS DM74LS IN74ALS HD74ALS SN74ALS SN74ALS SN74ALS 74ALS DM74ALS IW4 HD14 MC14 TC4

Contextual Info: HD151240 Octal Buffers / Line Drivers With 3 State Outputs The HD151240 using CMOS process, provides high speed and high drivability equivalent to HD74LS240 with super low power dissipation. The device has eight inverter drivers three state outputs in 20 pin package. Each four drivers

HD74LS151P

Abstract: 1S2074 HD74LS151 HD74LS151RPEL PRDP0016AE-B PRSP0016DG-A
Contextual Info: HD74LS151 1-of-8 Data Selector / Multiplexer with strobe REJ03D0497–0200 Rev.2.00 Feb.18.2005 This data selector / multiplexer contains full-on chip binary decoding to select the desired data source. The HD74LS151 selects one-of-eight data sources and has a strove input, which must be at a low logic level to enable this device. A high