HD74ALS Search Results
HD74ALS Datasheets (5)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| HD74ALS00P | Hitachi Semiconductor | Quad 2-Input Positive NAND Gate | Scan | 26.8KB | 1 | ||
| HD74ALS04P | Hitachi Semiconductor | Hex Inverter | Scan | 41.67KB | 2 | ||
| HD74ALS05P | Hitachi Semiconductor | Hex Inverter | Scan | 41.67KB | 2 | ||
| HD74ALS109P | Hitachi Semiconductor | Dual J-K Positive Edge Triggered Flip-Flops | Scan | 62.56KB | 2 | ||
| HD74ALS74P | Hitachi Semiconductor | Dual D-Type Positive Edge Triggered Flip-Flops | Scan | 61.95KB | 2 |
HD74ALS Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
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Contextual Info: HI T A C H I / LOGIC/ARRAYS/MEfl Sfl DÈI 4 4 ^ 2 0 3 0005541 T 58C 05241 HD74ALS03 •Quadruple 2 -input Positive NAND Gates with open collector outputs ~p L Lf IPIN ARRANGEMENT P" I *B (T op V iew ) •ELECTRICAL CHARACTERISTICS (Ta - 20— 1-75‘C) |
OCR Scan |
hd74als03--18ma | |
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Contextual Info: H I T A C H I / L O G I C / A R R A Y S / H E H Sñ D Ë | 4 4 ‘ìb2D3 0 0 0 5 E 4 4 4 |~ 58C 05 244 HD74ALS08 -r- 43 -/s ' •Quadruple 2-input Positive AND Gates ‘• P IN D arrangement T op V iew ¡ELECTRICAL CHARACTERISTICS (Ta Item Input voltage |
OCR Scan |
hd74als081s2074 | |
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Contextual Info: HITACHI/ LOGIC/ARRAYS/MEN Sfl D Ë J 44Sh2l]3 □ □ □ 5 2 4 ? □ 58C 05247 HD74ALS21 D - VJ -/s' #Dual 4-Input Positive AND Gates IPIN ARRANGEMENT Top View •ELECTRICAL CHARACTERISTICS (Ta Item Symbol 2 0~+75,C) T e s t Conditions min typ* - max Unit |
OCR Scan |
44sh2lhd74als21-----18ma | |
74ls series logic family
Abstract: SN74HC logic family CMOS 4000 TTL 74ALS CMOS 4000 Series family cmos logic 4000 series 74LS TTL 245 74ls TTL family 74ls series family cross reference cmos 4000
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Original |
hd74lssn74lsdm74lsin74als+12 | |
cmos logic 4000 series
Abstract: TTL 74ALS 74 series TTL NOT gate MM74HC CMOS 4000 Series family 74ls series logic family CMOS 4000 SN74HC logic family 74ls TTL family 74ALS
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Original |
hd74lssn74lsdm74lsin74als+12 | |
HD74LSContextual Info: ADVANCED LOW POWR SCHOTTKY TTL HD74ALS SERIES • HD74ALS00 ^ Quadruple 2-¡nput Positive N A N D Gafes • HD74ALS01 Quadruple 2-input Positive N A N D Gates with open collector outputs • HD74ALS03 Quadruple 2-input Positive N A N D Gates (with open collector outputs) |
OCR Scan |
hd74alshd74als00hd74als01hd74als03+7 | |
ALS04
Abstract: ALS05
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OCR Scan |
000sem2hd74als04hd74als05a--25+4 | |
74LS272
Abstract: 74LS series logic gates HD74LS 74ALS SERIES ic ttl 74ls 74ls gate symbols 74LS series logic gates 3 input or gate HD74ALS00 ECL IC NAND HD74ALS03
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OCR Scan |
hd74alshd74als00hd74als01hd74als03+14 | |
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Contextual Info: HITACHI/ L O G IC /A RR A YS/ ME N Sfl HD74ALS20 D Ë | 44c]t,2D3 □ 0 0 5 2 4 1. & | 58C 05246 #D u al 4-Input Positive NAND Gates - p V ß D - M 1 IPIN ARRANGEMENT l r" liD Top View ¡ELEC TRICA L CHA RA CTERISTICS ( T a - - 2 0 — h75"C) min typ* max |
OCR Scan |
hd74als20--50pf1s2074 | |
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Contextual Info: HD74ALS00 •Q u a d ru p le 2 - input Positive NAND Gates • P IN A R R A N G EM EN T ■ E L E C T R IC A L C H A R A C T E R IS T IC S Item Symbol V,H V,L Input voltage VOH Output voltage VOL Im I, IlL IoD IcCH Input c u rren t Output drive c u rren t |
OCR Scan |
hd74als001s2074 | |
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Contextual Info: HD74ALS04 •H e x Inverters HD74ALS05 #Hex Inverters with open collector outputs IPIN ARRANGEMENT ICIRCUIT SCHEMATICS (1/6) (Top V iew) ¡RECOMMENDED OPERATING CONDITIONS H D 74A L S04 min typ max High level output voltage Va -4 0 0 High level output c u rren t |
OCR Scan |
hd74als04hd74als05oh-----400m-----400m+2 | |
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Contextual Info: I I r% | | I A J g A I Dual D-type P ositi ve-edge-triggered Flip -Flop s with Preset and C lear ¡TIM IN G D EFIN IT IO N ¡F U N C T IO N T A B L E P r e s e t C le a r C lock D Q Q 3v L H X X H L ¡S 4 — H L X X L H L L X X H* H* H H Î H H L L L |
OCR Scan |
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lm358
Abstract: HA17324 LM324 LM339 LM358 CROSS REFERENCE LM393 LM339, KA339 lm358 cmos SN74HC cross reference lm358 jrc
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Original |
il324njm2902lm324ka324+13 | |
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Contextual Info: Ln iUr ^ /T H^ rAM IL OC 1I A O • D u a l J -K Positive-edge-triggered Flip-Flops W i t h Preset and C lear • PIN A R R A N G E M E N T ■ F U N C T IO N T A B L E Outputs Inputs P reset C lear Clock ÌC J Q Q H X L X X H L X X H L X L H L X X X H* |
OCR Scan |
1s2074 | |
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