74LS CHARACTERISTICS Search Results

F74B

Contextual Info: SPEED/PACKAGE AVAILABILITY 54 f ;w 54H F,W 54LS F,W 54S F,W 74 74H 74LS 74S PIN CONFIGURATION A,F A,F A,F A,F 74.74H, 54/74LS, 54/748 A,F,W PACKAGE SWITCHING CHARACTERISTICS TEST CONDITIONS PARAMETER 54,54« W PACKAGE v C C - 5V, TA = 25°C 54/74 54/74H 54/74LS

LS623

Abstract: D2537 SN74LS620
Contextual Info: S N 54LS 620, SN 54LS621, SN 74LS 620, SN 74LS 621, SM 74LS623 OCTAL BUS TRANSCEIVERS D2537, AUGUST 1979-REVISEO MARCH 1988 SN 54LS620, S N 54LS621, S N & 4 L S 6 2 2 . . . J P AC K A G E S N 74LS 620, S N 74LS621, S N 7 4 L S 6 2 3 . . . D W O R N P AC K A G E

Contextual Info: AVG DDi Semiconductors Technical Data 192, 193 Synchronous Up/Down Decade and Binary Counters with CLEAR DV74LS192 DV74ALS192 DV74LS193 DV74ALS193 The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary

Contextual Info: AVG DDi Semiconductors Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are

4QFC

Abstract: S62D
Contextual Info: SN54LS595, SN54LS596, SN74LS595, SN74LS596 8 BIT SH IFT REGISTERS W ITH O U TPU T LATC H ES 02634, JANUARY 1981 - REVISED MARCH 1988 S N 54LS 595, SN64LS596 . . . J OR W PACKAGE SN 74LS 595, S N 74LS 596 . . . N PACKAGE 8-Bit Serial-ln, Parallel-Out Shift

20-PIN

Abstract: M74LS37P
Contextual Info: MITSUBISHI LSTTLs M 74LS 37P Q U A D RU PLE 2-IN P U T P O S IT IV E NAND B U FFER DESCRIPTION The M 74LS 37P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing four 2-in p u t positive N A N D and negative NOR buffer gates. FEATURES

SN74LS604

Contextual Info: SN54LS604, SN54LS606, SN54LS607, SN74LS604, SN74LS606, SN74LS607 OCTAL 2-INPUT MULTIPLEXED LATCHES D254-5, JULY 1979-REVISED MARCH 1988 T IM 9 9 6 0 4 , T IM 9 9 6 0 6 , T IM 9 9 6 0 7 SN 54LS 604, SN 54LS 606, SN 54LS607 . . JO PACKAGE SN 74LS 604, SN 74LS 606. SN 74LS607 . . . JD OR N PACKAGE

mitsubishi air conditioning

Abstract: 20-PIN M74LS51P Scans-000 74ls51p
Contextual Info: MITSUBISHI LSTTLs M 74LS 51P DUAL 2 -W ID E 2 -IN P U T /3 -IN P U T AND -O R -IN VER T GATE DESCRIPTION The M 74LS 51P is a semiconductor integrated PIN CONFIGURATION TOP VIEW circuit containing dual 2-wide 2-in p u t/3 -in p u t A N D -O R -IN V E R T

AF001140

Abstract: AM25LS2513
Contextual Info: eiszsiszmv Am25LS2513 Three-State Priority Encoder DISTINCTIVE CHARACTERISTICS • • • Encodes eight lines to three-line binary Expandable Cascadable Three State inverted output version of Am54LS/74LS/ 25LS148 Gated three-state output Advanced Low-Power Schottky processing

Am2913

Contextual Info: Am2913 Am 2913 Priority Interrupt Expander DISTINCTIVE CHARACTERISTICS • • • Similar in function to Am54LS/74LS/25LS148/2513 Gated three-state output Advanced Low-Power Schottky processing Encodes eight lines to three-line binary Expands use of Am2914

Contextual Info: A m 2 5L S 2 51 3 Three-State Priority Encoder DISTINCTIVE CHARACTERISTICS • • Three State inverted output version of Am54LS/74LS/ 25LS148 Gated three-state output Advanced Low-Power Schottky processing Encodes eight lines to three-line binary Expandable

HK-5-G

Abstract: 50/Am2913
Contextual Info: Am2 913 Priority Interrupt Expander DISTINCTIVE CHARACTERISTICS • • • Encodes eight lines to three-line binary Expands use of Am2914 Cascadable • Similar in function to Am54LS/74LS/25LS148/2513 • Gated three-state output • Advanced Low-Power Schottky processing

D74LS

Abstract: D74LS08
Contextual Info: H D 74LS 08 •Quadruple 2-input Positive AND Gates •PIN ARRANGEMENT ¡CIRCUIT S C H E M A T IC ^ ■ELECTRICAL CHARACTERISTICS T a = - 2 0 ~ +75"C ) Item Input voltage Symbol Test Conditions min - V lL - - 0 .8 V 2.7 - - V - - 0.5 - - - - V cc = 4.75V ,

74ls166

Abstract: 74ls gate symbols 74LS TTL 74ls166 datasheet 74LS LS166 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS166 8-BIT SHIFT REGISTERS The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54/ 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and

Altera EP1800

Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
Contextual Info: EP1800 Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conventional and custom logic. Speed equivalent to 74LS TTL with 25 MHz clock rates. “Zero Power” typically 10/jA standby . Active power of 250 mW at 5 MHz.

SN74LS166d

Abstract: sn74ls166
Contextual Info: SN74LS166 8−Bit Shift Registers The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified.

4 bit even and odd parity checker

Abstract: 20-PIN M74LS280P 4 bit even parity generator circuit
Contextual Info: MITSUBISHI LSTTLs M74LS280P 9 -B IT ODD/EVEN PARITY GENERATOR/CHECKER DESCRIPTION The M 74LS 280P is a semiconductor integrated circuit containing a 9-b it parity generator/checker function. FEATURES • Easy expansion of bits w ith cascade connection •

54ls640

Contextual Info: SN54LS640 THRU SN54LS642, SN54LS644. SNS4LS645 SN74LS640 THRU SN74LS642, SN74LS644, SN74LS645 OCTAL BUS TRANSCEIVERS D2420, APRIL 1979-REV1SED MARCH 1988 SN54LS' . . . J PACKAGE SN 74LS' . . . DW OR N PACKAGE SN74LS04X-1 Versions Rated at I qj_ of 48 mA TOP VIEW

SN74LS166

Abstract: 74LS LS166 SN74LS166D SN74LS166DR2 SN74LS166M SN74LS166MEL SN74LS166N
Contextual Info: SN74LS166 8-Bit Shift Registers The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified.

74LS90P

Abstract: M74LS90P 20-PIN M74LS290P
Contextual Info: MITSUBISHI LSTTLs M74LS90P DECADE COUNTER DESCRIPTION The M 74LS 90P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing an asynchronous decade counter function w ith direct reset inputs and direct 9-set inputs. • Direct reset inputs provided

SN74LS383

Contextual Info: TYPES SN54LS363. SN54LS364. SN74LS363, SN741S364 OCTAL D-TYPE TRANSPARUT IATCMESAND ED6E-TRI6CEBED FUP-FlOPS TTL MSI BULLETIN HO. OL-& 7*11*6«, OCTOBiR 107« • SNMLS363 . . . J PACKAGE SN74LS383 . . . J OR N PACKAGE TOP VIEW High VOH •• ■3.65 V Min ( 74LS')

Contextual Info: GD54/74HC157, GD54/74HCT157 QUAD 2-INPUT SELECTORS/MULTIPLEXERS WITH NONINVERTED OUTPUT General Description Pin Configuration These devices are identical in pinout to the 54/74LS 157. They consist of four 2-input multiplex­ ers with common select and enable inputs, and

54HCT564

Abstract: 74HCT 74HCT564
Contextual Info: MM54/74HCT564 v National Semiconductor microCMOS MM54HCT564/MM74HCT564 TRI-STATE Octal D-Type Flip-Flop with Inverted Outputs General Description The 54HCT/74HCT logic family is speed, function, and pin­ out compatible with the’ standard 54LS/74LS logic family.

74L86

Contextual Info: SN54LS386A, SN74LS386A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES MARCH 1974 - REVISED MARCH 198B SN 54LS 386A . . . J OR W PACKAGE SN 74LS 386A . . . D OR N PACKAGE Electrically Identical to SN54LS86A/SN74LS86A TOP VIEW Mechanically Identical to SN 54L86/S N 74L86