74LS CHARACTERISTICS Search Results

F74B

Contextual Info: SPEED/PACKAGE AVAILABILITY 54 f ;w 54H F,W 54LS F,W 54S F,W 74 74H 74LS 74S PIN CONFIGURATION A,F A,F A,F A,F 74.74H, 54/74LS, 54/748 A,F,W PACKAGE SWITCHING CHARACTERISTICS TEST CONDITIONS PARAMETER 54,54« W PACKAGE v C C - 5V, TA = 25°C 54/74 54/74H 54/74LS

LS623

Abstract: D2537 SN74LS620
Contextual Info: S N 54LS 620, SN 54LS621, SN 74LS 620, SN 74LS 621, SM 74LS623 OCTAL BUS TRANSCEIVERS D2537, AUGUST 1979-REVISEO MARCH 1988 SN 54LS620, S N 54LS621, S N & 4 L S 6 2 2 . . . J P AC K A G E S N 74LS 620, S N 74LS621, S N 7 4 L S 6 2 3 . . . D W O R N P AC K A G E

Contextual Info: AVG DDi Semiconductors Technical Data 192, 193 Synchronous Up/Down Decade and Binary Counters with CLEAR DV74LS192 DV74ALS192 DV74LS193 DV74ALS193 The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary

Contextual Info: AVG DDi Semiconductors Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are

IC 74LS14

Abstract: 74ls14 74LSxx ic 74ls13
Contextual Info: M OTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The S N 54LS /74LS 13 and SN 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into

LS748

Abstract: 74LS147 74LS148 74lS748
Contextual Info: g MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the SN 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order

Contextual Info: 25LS194A 4-Bit Universal Shift Register 25LS195A 4-Bit Parallel-Access Shift Register FEATURES • ■ PIN-OUT DIAGRAM Higher speed compared to 9LS/54LS and 9LS/74LS 8mA sink current over full military temperature range ■ 50m V improved V o l compared to 9LS/74LS

4QFC

Abstract: S62D
Contextual Info: SN54LS595, SN54LS596, SN74LS595, SN74LS596 8 BIT SH IFT REGISTERS W ITH O U TPU T LATC H ES 02634, JANUARY 1981 - REVISED MARCH 1988 S N 54LS 595, SN64LS596 . . . J OR W PACKAGE SN 74LS 595, S N 74LS 596 . . . N PACKAGE 8-Bit Serial-ln, Parallel-Out Shift

Contextual Info: MOTOROLA SN54/74LS168 SN54/74LS169 BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN 54/74LS 168 and SN 54/74LS 169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U /D input to control the direction

ls190

Abstract: 30132 10116
Contextual Info: 190,191 AVG Semiconductors DDT Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are

20-PIN

Abstract: M74LS37P
Contextual Info: MITSUBISHI LSTTLs M 74LS 37P Q U A D RU PLE 2-IN P U T P O S IT IV E NAND B U FFER DESCRIPTION The M 74LS 37P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing four 2-in p u t positive N A N D and negative NOR buffer gates. FEATURES

74LS299 APPLICATIONS

Contextual Info: M MOTOROLA SN54/74LS323 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The S N 54/74LS 323 is an 8-Bit Universal S hift/S torage Register with 3-state outputs. Its function is sim ilarto the SN 54/74LS 299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are

Contextual Info: M MOTOROLA SN54/74LS490 DUAL DECADE COUNTER The S N 54/74LS 490 contains a pair of high-speed 4-stage ripple counters. Each half of the S N 54/74LS 490 has individual Clock, Master Reset and Mas­ ter Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.

74LS18P

Contextual Info: MITSUBISHI LSTTLs M 74LS 18P DUAL 4-IN P U T NAND SCHMITT TRIGGER DESCRIPTION The M 74LS 18P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing tw o 4-input positive-logic N A N D gates having a schm itt trigger function and negative-logic N O R gates.

SN74LS604

Contextual Info: SN54LS604, SN54LS606, SN54LS607, SN74LS604, SN74LS606, SN74LS607 OCTAL 2-INPUT MULTIPLEXED LATCHES D254-5, JULY 1979-REVISED MARCH 1988 T IM 9 9 6 0 4 , T IM 9 9 6 0 6 , T IM 9 9 6 0 7 SN 54LS 604, SN 54LS 606, SN 54LS607 . . JO PACKAGE SN 74LS 604, SN 74LS 606. SN 74LS607 . . . JD OR N PACKAGE

Contextual Info: M M O T O R O L A SN54/74LS168 SN54/74LS169 BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN 54/74LS 168 and SN 54/74LS 169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U /D input to control the direction

74ls795

Abstract: 74LS796 74ls797
Contextual Info: M MOTOROLA SN54/74LS795 SN54/74LS796 SN54/74LS797 SN54/74LS798 TRI-STATE OCTAL BUFFERS The S N 54/74LS 795 thru S N 54/74LS 798 device types provide a second source for the 71 /8 1 LS95 thru 7 1 /8 1 LS98 series. These devices are octal low power Schottky versions of the 70/8095 thru 70/8098 3-STATE Hex

mitsubishi air conditioning

Abstract: 20-PIN M74LS51P Scans-000 74ls51p
Contextual Info: MITSUBISHI LSTTLs M 74LS 51P DUAL 2 -W ID E 2 -IN P U T /3 -IN P U T AND -O R -IN VER T GATE DESCRIPTION The M 74LS 51P is a semiconductor integrated PIN CONFIGURATION TOP VIEW circuit containing dual 2-wide 2-in p u t/3 -in p u t A N D -O R -IN V E R T

74ls series logic family

Abstract: SN74HC logic family CMOS 4000 TTL 74ALS CMOS 4000 Series family cmos logic 4000 series 74LS TTL 245 74ls TTL family 74ls series family cross reference cmos 4000
Contextual Info: INTEGRAL KOREA Cross Reference Characteristics Technology IK Semi Hitachi IN74 TTL CMOS 4000 On Semi Toshiba TI Philips Fairchild SN74 SN74 SN74 74 DM74 IN74LS HD74LS SN74LS SN74LS SN74LS 74LS DM74LS IN74ALS HD74ALS SN74ALS SN74ALS SN74ALS 74ALS DM74ALS IW4

AF001140

Abstract: AM25LS2513
Contextual Info: eiszsiszmv Am25LS2513 Three-State Priority Encoder DISTINCTIVE CHARACTERISTICS • • • Encodes eight lines to three-line binary Expandable Cascadable Three State inverted output version of Am54LS/74LS/ 25LS148 Gated three-state output Advanced Low-Power Schottky processing

cmos logic 4000 series

Abstract: TTL 74ALS 74 series TTL NOT gate MM74HC CMOS 4000 Series family 74ls series logic family CMOS 4000 SN74HC logic family 74ls TTL family 74ALS
Contextual Info: z Cross Reference Characteristics Technology IK Semi Hitachi IN74 TTL CMOS 4000 On Semi Toshiba TI Philips Fairchild SN74 SN74 SN74 74 DM74 IN74LS HD74LS SN74LS SN74LS SN74LS 74LS DM74LS IN74ALS HD74ALS SN74ALS SN74ALS SN74ALS 74ALS DM74ALS IW4 HD14 MC14 TC4

Am2913

Contextual Info: Am2913 Am 2913 Priority Interrupt Expander DISTINCTIVE CHARACTERISTICS • • • Similar in function to Am54LS/74LS/25LS148/2513 Gated three-state output Advanced Low-Power Schottky processing Encodes eight lines to three-line binary Expands use of Am2914

Contextual Info: A m 2 5L S 2 51 3 Three-State Priority Encoder DISTINCTIVE CHARACTERISTICS • • Three State inverted output version of Am54LS/74LS/ 25LS148 Gated three-state output Advanced Low-Power Schottky processing Encodes eight lines to three-line binary Expandable

HK-5-G

Abstract: 50/Am2913
Contextual Info: Am2 913 Priority Interrupt Expander DISTINCTIVE CHARACTERISTICS • • • Encodes eight lines to three-line binary Expands use of Am2914 Cascadable • Similar in function to Am54LS/74LS/25LS148/2513 • Gated three-state output • Advanced Low-Power Schottky processing