133FI Search Results

PALCE22v10 amd

Contextual Info: a PALCE22V1 OH-15/25/Q-25 Advanced Micro Devices 24-pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS • As fast as 15 ns propagation delay and 50 MHz fMAx ■ Global asynchronous reset and synchronous preset for initialization ■ Low-power EE CMOS

33F2

Abstract: l62a marking 133I 1N3064
Contextual Info: MIL-M-38510/162A fiÆaiwæ- IQ U A L I F I C A T I M I REQUIREMENTS I I R E M OV E D I MIL-M-38510/162(USAF 2 A u gu st 1976 MILITARY SPECIFICATION M I C R O C I R C U I T S , D I G I T A L , T T L , N OR B U F F E R S , M ON OL IT HIC SILICON j INACT I VE F OR NEW D E S I G N A F T E R DA T E OF T H I S R E V I S I O N j

Contextual Info: June 1992 DM74S240, DM74S241, DM74S244 Octal TRI-STATE Buffer/Line Driver/Line Receiver General Description Typical Io l sink current 74S 64 mA Typical Ioh (source current) 74S - 1 5 mA Typical propagation delay times Inverting 4.5 ns Noninverting 6 ns

F74B

Contextual Info: SPEED/PACKAGE AVAILABILITY 54 f ;w 54H F,W 54LS F,W 54S F,W 74 74H 74LS 74S PIN CONFIGURATION A,F A,F A,F A,F 74.74H, 54/74LS, 54/748 A,F,W PACKAGE SWITCHING CHARACTERISTICS TEST CONDITIONS PARAMETER 54,54« W PACKAGE v C C - 5V, TA = 25°C 54/74 54/74H 54/74LS

SN7441

Abstract: 74L78 Sw 7441Aj SN7401 SN7449 7475n itt u6a9601 N8490 National Semiconductor Linear Data Book c2003p
Contextual Info: TTL Integrated Circuits Catalog from Texas Instruments 1 August 1969 T e x a s In s t r u m e n t s IN C O R P O R A T E D P O S T O F F IC E B O X 5 0 1 2 • D ALLAS. TEXAS 75222 GENERAL INFORMATION INDEXES Numerical • Functional • Cross-Reference TTL APPLICATION REPORTS

690c

Contextual Info: ^W \ National À j Ì Semiconductor DM74AS640 TRI-STATE Octal Bus Transceiver General Description Features This advanced Schottky device contains 8 pairs of TRI­ STATE logic elements configured as octal bus transceiver. This circuit is designed for use in memory, microprocessor

74LS210

Abstract: SN74LS210 SN54/74LS210 SN74S210 42A12A 74S210 2y2e
Contextual Info: 8-Bit Buffers SN 54/74LS210 S N 54/74S 210 S N 5 4 /7 4 L S 2 4 0 S N 5 4 /7 4 L S 2 4 1 S N 5 4 /7 4 L S 2 4 4 S N 5 4 /7 4 S 2 4 0 S N 5 4 /7 4 S 2 4 1 S N S 4 /7 4 S 2 4 4 Ordering Information Features/ Benefits • Three-slate outputs drive bus lines PART

6513

Abstract: DM5438J DM5438W DM7438M DM7438N J14A M14A N14A W14B
Contextual Info: June 1989 DM5438/DM7438 Quad 2-Input NAND Buffers with Open-Collector Outputs Pull-Up Resistor Equations General Description V çç Min - Vpn This device contains lour independent gates each of which performs the logic NAND function. The open-collector out­

DM7437N

Abstract: 5437DMQB 5437FMQB DM5437J DM5437W J14A N14A W14B 5437DM
Contextual Info: , June 1989 5437/DM5437/DM7437 Quad 2-Input NAND Buffers General Description Features This device contains lour independent gates each of which performs the logic NAND function. • Alternate Military/Aerospace device 5437 is available, Contact a National Semiconductor Sales Office/Distrib­

74LS340

Abstract: ls344 74ls344 74ls341 LS340 74LS210 74LS34 IC 74LS14 replacement 74LS31 74LS310
Contextual Info: 8 -B it Buffers w ith Schm itt Trigger Inputs Features S N 5 4 /7 4 L S 3 1 0 S N 5 4 /7 4 L S 3 4 0 S N 5 4 /7 4 L S 3 4 1 S N 5 4 /7 4 L S 3 4 4 S N 5 4 /7 4 S 3 1 0 S N 5 4 /7 4 S 3 4 0 S N 5 4 /7 4 S 3 4 1 S N 5 4 /7 4 S 3 4 4 Ordering Inform ation • Schmitt-trigger inputs guarantee high noise margin

A17A

Abstract: A15A a17b diode A14A A11A A13A A14A AS9C25128M2036L AS9C25256M2036L be0b
Contextual Info: September 2004 Preliminary Information AS9C25256M2036L AS9C25128M2036L 2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface Features • True Dual-Port memory cells that allow simultaneous access of the same memory location • Organisation: 262,144/131,072 x 36[1]

A17a

Abstract: a17b A18B-A0B diode A14A A14A A15A A16A AS9C25256M2018L AS9C25512M2018L DQ17A
Contextual Info: September 2004 Preliminary Information AS9C25512M2018L AS9C25256M2018L 2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface Features • True Dual-Port memory cells that allow simultaneous access of the same memory location • Organisation: 524,288/262,144 x 18[1]

Contextual Info: Semiconductor August 1989 54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers General Description These buffers/line drivers are designed to improve both the performance and PC board density of TRI-STATE buffers/ drivers employed as memory-address drivers, clock drivers,

A13B

Abstract: DQ17A-DQ0A A14B DQ4a DQ11A
Contextual Info: July 2004 Preliminary Information AS9C25512M2018L 2.5V 512K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface Features • True Dual-Port memory cells that allow simultaneous access of the same memory location • Organisation: 524,288 x 18 bits

SN7441

Abstract: 54175 TFK 404 MM1402a equivalent SD300 N74141 SN7401 3 BB 4 SO 5 CON 6 RAY 7 CC 8 SI 9 RB 10 RG 11 VE
Contextual Info: NUMERICAL INDEX FUNCTIONAL INDEX SALES OFFICES Copyright 1974 S IG N E T IC S C O R P O R A T IO N Signetics Corporation reserves the right to make changes in the products contained in this book in order to improve design or performance and to supply the best possible product.

ITT Cannon cct

Abstract: 4h27 CHP-420
Contextual Info: o SUBMINIATURE RECTANGULAR CONNECTORS ITT CANNON CONNECTOR SELECTION GUIDE Continued CONNECTORS FOR PRINTED CIRCUIT BOARDS SHIELDED RIGHT ANGLE EDBL25SBA1 ED* Series Page 17 PIN AND SOCKET RIGHT ANGLE DDP-50SAA 0* P Series Page 20 VERTICAL MOUNT DBPF25 (P or S) Y4