74LS6 Search Results

74ls610

Abstract: D2549 74LS612 SN74LS610 TMS9900 LS610
Contextual Info: SN54LS610, SN54LS612, 74LS610 THRU 74LS613 MEMORY MAPPERS D2549, JANUARY 1 98 1 -REVISED MARCH 1988 • Expands 4 Address Lines to 12 Address Lines S N 5 4 L S ' . . . J D P AC K A G E SN74LS' . JD OR N P AC K A G E TO P VIE W • Output Latches Provided on 'LS610 and

N74LS642N

Abstract: ls642
Contextual Info: Sìgnetics 74LS641, LS642, 74LS641-1, LS642-1 Transceivers Octal Bus Transceiver Open Collector Product Specification Logic Products FEATURES • Octal bidirectional bus interface • Open Collector Outputs — 'LS641, non-inverting — 'LS642, inverting

M74LS684P

Abstract: 8BIT MAGNITUDE COMPARATOR M74LS682P M74LS683P M74LS685P M74LS688P M74LS689P
Contextual Info: MITSUBISHI LSTTLs ^ M 74LS684P S -B IT M A G N ITU DE COMPARATOR DESCRIPTION T h e M 7 4 L S 6 8 4 P is a s em ico n d u c to r in teg rated c irc u it c o n ­ PIN CONFIGURATION TOP VIEW ta in in g tw o 8 -b it w o rd s c o m p a ra to r fu n ctio n s .

register file

Abstract: LS670 74LS670 74LSI70
Contextual Info: Am25LS670 • Am54LS/74LS670 4-By-4 Register File with 3-State or Open Collector Outputs Am25LS670 • Am54LS/74LS670 data is combined with the Am25LS170. See Am25LS170 data sheet for full information. F U N C T IO N A L DESCRIPTION T h e A m 2 5 L S 1 7 0 and 6 7 0 are 1 6 -b it lo w -p o w e r S c h o tt k y

panasonic tsu

Abstract: fmu 22 u 251C
Contextual Info: PANASONIC INDL/ELEK -CIO 752 6 9 3 2 8 52 P AN ASO N JC dË | [3=132052 00Q72&1 b I N O L « E l EÇ T R O t y I Ç _ _ 7 2 Ç .0 .7 .2 6 1 LS TTL DN74LSS>U-X D T-45-23-09 74LS668/74LS668S DN 74LS668/ DN 74LS668S Synchronous U p/D ow n D ecade C ounter

LS645

Abstract: 74ls642 SN54/74LS642 SN54LSXXXJ LS640 LS641 LS642 74LS645 8A79 74LS641
Contextual Info: SN54/74LS640 SN54/74LS641 SN54/74LS642 SN54/74LS645 OCTAL BUS TRANSCEIVERS These octal bus transceivers are designed for asynchronous two-way communication between data buses. Control function implementation minimizes external timing requirements. These circuits allow data transmission from the A bus to B or from the B bus to A bus depending upon the logic

motorola 74LS670

Abstract: Dip 28 motorola 74LS170 74LS670 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS670 4 x 4 REGISTER FILE WITH 3-STATE OUTPUTS The TTL / MSI SN54 / 74LS670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

74157 pin diagram

Abstract: TTL 74153 74s157 pin diagram fairchild 9312 74157 D157 Fairchild 9322 93L09 74S153 93L22
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL - T T L D154 54/74170, 54LS/74LS170, 54LS/74LS670 15 H 1 2 3 12 11 10 I M Ew Ü2 Dl D3 loa I la 1 3 - W b 1 3 - So 5 - Ra 3 - S i N T 14 11 10 6 T 7 E lo 11 3 3 5 6 S 11— 0 CP 7 lOb 11b lOc l i e

Contextual Info: SN54/74LS640 SN54/74LS641 SN54/74LS642 SN54/74LS645 OCTAL BUS TRANSCEIVERS These octal bus transceivers are designed for asynchronous two-way communication between data buses. Control function implementation minimizes external timing requirements. These circuits allow data transmission from the A bus to B or from the B bus to A bus depending upon the logic

74LS645

Abstract: 54LS SN54LS645 SN74LS645-1
Contextual Info: FOR MORE DETAIL SEE SECTION 8-Bit Buffer Transceiver SN54/74LS645 74LS645-1 1 3 Features/ Benefits Ordering Information • Three-stale outputs drive bus lines • Low current PNP Inputs reduce loading • Symmetric — equal driving capability In each direction

74243

Abstract: 74LS621 74LS623
Contextual Info: Quad 3-State Bus Transceivers 8 bit S f i t l t 74LS621, 74LS623 iy h & ms * 'J ' A ? tpd «ax L-H tpd max H-*L T i 18 11 11 6 .2 9 6. 5 9 tpd max Z— L V 30 20 21 8.5 15 tpd max Z-*H A 23 20 19 6. 7 12 tpd nax L-Z T 25) 22 8 7 tpd nax H-*Z ▲ (18) 14

74LS643

Abstract: 74LS643-1 74ALS643 74245 rca 645 BC 641 74643 84 JRC 74LS639 74LS640
Contextual Info: - 278- 74643 VCC DIR Octal 3-State Bus Transceiver C 81 A1 A2 62 A3 83 84 06 66 A4 A5 A6 A7 74LS643-1, 74ALS643-1 l i 74ALS1643-1 l± I o l 24mA 87 88 AS GNO Io l 48mA F U N C T IO N T A B L E CO NTROL OPERATION INPUTS 638 640 639 641 643 m a *'j' x-n tpd

Contextual Info: 8-Bit Buffer Transceiver SN54/74LS645 FOR MORE DETAIL S E E SECTION 74LS645-1 Features/ Benefits 13 Ordering Information • Three-state outputs drive bus lines • Low current PNP inputs educe loading • Symmetric — equal driving capability In each direction

74LS60

Contextual Info: LS TTL DN74LS Series DN74LS260 DN74LS260 Dual 5 -input P o sitiv e NOR Gates • Description D N 74LS60 c o n ta in s P-1 tw o 5 -in p u t p o sitiv e-lo g ic NOR g ate c irc u its. ■ Features • L o w p o w e r c o n s u m p tio n P d = 2 0 m W ty p ic a l

74ls82

Abstract: 74LS820 ls623 74LS623 LS620 1N3064 1N916 74LS 74LS620 N74LS620N
Contextual Info: 74LS620, LS623 Signetics Transceivers 'LS620 Inverting Octal Bus Transceiver 3-State 'LS623 Non-Inverting Octal Bus Transceiver (3-State) Product Specification Logic Products FEATURES • O c ta l b id ire c tio n a l bu s In te rfa c e • 3 -S ta te b u ffe r o u tp u ts

L203

Abstract: 74LS670 SP74HCT670J SP74HCT670N
Contextual Info: SP74HCT670 PIN CONFIGURATION 4 -BY-4 REGISTER FILE FEATURES • ■ ■ ■ ■ ■ ■ Designed for high speed buffer storage Typical access time: 25 nSec Simultaneous Read/Write Operation Expandable to 512 words of n bits Pin and level compatible with 74LS670

SN74LS83

Abstract: SN54LS638 SN54LS639 SN74LS SN74LS638 SN74LS639 LS638
Contextual Info: SN54LS638, SN54LS639, 74LS638. 74LS639 OCTAL BUS TRANSCEIVERS D2636, JANUARY 1981 -REVISED MARCH 1988 Bidirectional Bus Transceivers in HighDensity 20-Pin Packages SN54LS638, SN 54LS639 . . . J PACKAGE S N 74LS638. SN 74LS 639 . . . DW OR N PACKAGE TOP VIEW

LP3J

Abstract: 74LS682
Contextual Info: M MOTOROLA SN54LS/74LS682 thru SN54LS/74LS689 D E S C R IP T IO N — The S N 5 4 L S /7 4 L S 6 8 2 th ru S N 5 4 L S /7 4 L S 6 8 9 a re 8 -b it m a g n itu d e c o m p a ra to rs . The se dev ic e ty p e s are de s ig n e d to p e rfo rm c o m p a ris o n s b e tw e e n tw o e ig h t b it b in a ry o r BCD w o rd s . A ll

5BA DIODE

Contextual Info: g MOTOROLA D ESC RIP TIO N — The SN54LS/74LS623 series is an octal bus trans­ ceiver designed for asynchronous two-way communication between data buses. Control function implementation allows m axim um tim­ ing flexibility. Enable inputs m ay be used to disable the device so

74LS674

Contextual Info: M MOTOROLA SN54LS/74LS673 SN54LS/74LS674 D E S C R IP T IO N — T he S N 5 4 L S /7 4 L S 6 7 3 and S N 5 4 L S /7 4 L S 6 7 4 are 3 -s ta te 1 6 -b it s h ift registers. T he L S 6 7 3 is a 1 6 -b it s h ift re g is te r and a 1 6 -b it sto ra g e re g is te r in a

mitsubishi cab

Contextual Info: MITSUBISHI LSTTLs M 74LS620P OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION The 74LS620P is a semiconductor integrated circuit containing an octal bus transmitter /receiver with a tri-state inverted output. PIN CONFIGURATION (TOP VIEW)

74LS682

Contextual Info: g MOTOROLA SN54/74LS682 SN54/74LS684 SN54/74LS688 8-BIT MAGNITUDE COMPARATORS The SN54/74LS682, 684, 688 are 8-bit magnitude comparators. These device types are designed to perform comparisons between two eight-bit binary or BCD words. All device types provide P = Q outputs and the LS682

751B-03

Contextual Info: MOTOROLA SN54/74LS670 4 x 4 REGISTER FILE WITH 3-STATE OUTPUTS The T T L/M S I S N 54/74LS 670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and w rite inputs, both address and enable, allow simultaneous read and write operation.

Contextual Info: M MOTOROLA SN54/74LS640 SN54/74LS641 SN54/74LS642 SN54/74LS645 OCTAL BUS TRANSCEIVERS These octal bus transceivers are designed tor asynchronous two-way communication between data buses. Control function implementation minimizes external timing requirements. These circuits allow data transmis­