74HCT139 Search Results

Contextual Info: [ /Title CD74 HC139 , CD74 HCT13 9 /Subject (High Speed CMOS Logic Dual 2-to-4 Line Decod CD54/74HC139, CD54/74HCT139 Data sheet acquired from Harris Semiconductor SCHS148B High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer September 1997 - Revised May 2000

PC 74HC139

Contextual Info: [ /Title CD74 HC139 , CD74 HCT13 9 /Subject (High Speed CMOS Logic Dual 2-to-4 Line Decod CD54/74HC139, CD54/74HCT139 Data sheet acquired from Harris Semiconductor SCHS148B High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer September 1997 - Revised May 2000

74HC139

Abstract: T139
Contextual Info: Technical Data CD54/74HC139 CD54/74HCT139 F ile N u m b e r 1545 High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer T y p e Features: • M u ltifu n c tio n C a pa bility B in a ry to 1-of-4 D ecoders or 1-to-4 Line D em u ltip le xe r ■ A ctive Low M u tu a lly E xclusive O utputs

74HCT139

Contextual Info: TECHNICAL DATA IN74LV139 Dual 2-to-4 line decoder/demultiplexer; inverting N SUFFIX PLASTIC The IN74LV139 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HCT139. The74LV139 is dual 2-to-4 line decoder/demultiplexer . This device has two independent decoders, each accepting two binary

Contextual Info: GD54/74HC139, GD54/74HCT139 DUAL 2-TO-4 LINE DECODER/DEMULTIPLEXER General Description These devices are identical in pinout to the 54/74L S 1 39. They contain two independent 1-of-4 decoders each with a single active-low enable in­ put. Each circuit decodes a 2-bit address to 1 -of-4

74HCT139

Abstract: KK74LV139 KK74LV139D KK74LV139N
Contextual Info: TECHNICAL DATA KK74LV139 Dual 2-to-4 line decoder/demultiplexer; inverting The KK74LV139 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HCT139. The74LV139 is dual 2-to-4 line decoder/demultiplexer . This device has two independent decoders, each accepting two binary weighted

74HC139

Abstract: pin diagram of 2 to 4 decoder 74ls139 decoder pin configuration 74hct139 74HC GD54HC139 GD74HC139
Contextual Info: GD54/74HC139, GD54/74HCT139 DUAL 2-TO-4 LINE DECODER/DEMULTIPLEXER General Description Pin Configuration Œ 1A [T U 1B p r Tï] 2A TTj 2 b 1Ÿ0 [ T 13 9 military specifications. Til vcc 1LÜ 1? ¿L T h e s e d evices are identical in pinout to the 5 4 /7 4 L S 1 3 9 . They contain tw o independent 1 -of-4

Contextual Info: J S f IDT54/74HCT139 CMOS DUAL 1-0F-4 DECODER Integrated Device Technology Inc in T 7 9 T 'V t ä IU I CN] CO LO FEATURES • • • • • • • • • High speed, comparable to bipolar: 9ns typ. CMOS low power levels: 50 typ. Inputs and outputs directly TTL-compatible

IC 74hct139

Abstract: 20 PIN LEADLESS CHIP CARRIER 74LS373 Decoder 8251A 1N916 74hct139
Contextual Info: HIGH SPEED CMOS DUAL 1-OF-4 DECODER Integrated Dev ice Technology. Inc IDT54/74HCT139 IDT72T339 i cr> CN CO FEATURES data-routing applications requiring very short propagation delay tim es, but needing very low power consum ption. The ID T 54/74H C T139 is pin and functionally com patible

74HC139

Abstract: CD4556B CD54HC139 CD54HCT139 CD74HC139 hct139 harris PC 74HC139
Contextual Info: U g 3 iZ J i6 5 Technical Data CD54/74HC139 CD54/74HCT139 F ile N u m b e r 4302271 0G17SÔ1 4 BIHAS 57E D HARRIS SEMICOND SECTOR 1545 High-Speed CMOS Logic AO . 2 114 3 03) Dual 2-to-4 Line Decoder/Demultiplexer 4 12Ï T y p e Featu res: • M u ltifu n c tio n C ap a b ility

irf 1740

Abstract: irf 729 74HCT14N 74HCT14D IRF 1470 irf 1205 74HCT373N AD1403AN ad693aq 74HCT74N
Contextual Info: Semiconductor Directory Mfr.Õs Type 13 Price Mfr.Õs Code Page Mfr.Õs Type Price Mfr.Õs Code Page Mfr.Õs Type Price Mfr.Õs Code Page Mfr.Õs Type Price Mfr.Õs Code Page 74HCT138N 74HCT139N 74HCT14D 74HCT14N 74HCT151N 0.40 0.37 0.17 0.54 0.41 PHI PHI

M74HCT13

Contextual Info: f Z 7 S G S -T H O M S O N Ä 7 # M 0 » H [L H « ! M54HCT139 M 74HCT139 DUAL 2 TO 4 DECODER/DEMULTIPLEXER • HIGHSPEED tpD = 17 ns (TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Icc = 4 |jA (MAX.) AT Ta = 25 "C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN.) Vil = 0.8V (MAX)

ic 74hct139

Abstract: 74HCT MD54HCT139RC MD74HCT139RE
Contextual Info: MD54/74HCT139R Dual 1 of 4 Decoder/Demultiplexer February '85 Features CONNECTION DIAGRAM DIP TO P VIEW • High latch-up immunity Ea c 1 16 A fla L 2 15 ^1a C 3 14 ^ •High current outputs can drive 15 LSTTL loads 13 ^ 12 11 ^ Oob ^ o lb c 7 c 8 10 3 o 2b

74HC139

Abstract: 74ls139 decoder pin configuration 74ls139 decoder
Contextual Info: GD54/74HC139, GD54/74HCT139 DUAL 2-TO-4 LINE DECODER/DEMULTIPLEXER General Description These d evices are identical in pinout to the Pin Configuration 5 4 /7 4 L S 1 3 9 . T hey contain tw o independent 1 -of-4 active-low outputs. Data on the se lec t inputs A, B

Contextual Info: Technical Data CD54/74HC139 CD54/74HCT139 F ile N u m b e r 1545 High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer Type Features: • M u ltifu n c tio n C a pa bility B in a ry to 1-of-4 D ecoders or 1-to-4 Line D em u ltiplexer • A ctive Low M u tu a lly E xclusive O utputs

CI 74HC139

Abstract: DHVQFN16 74HC139 74HCT139 74LV139 74LV139D 74LV139N JESD22-A114E SSOP16 NXP 74HC139
Contextual Info: 74LV139 Dual 2-to-4 line decoder/demultiplexer Rev. 04 — 13 December 2007 Product data sheet 1. General description The 74LV139 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC139 and 74HCT139. The 74LV139 is a dual 2-to-4 line decoder/demultiplexer. It has two independent

Contextual Info: MD54/74HCT139R Dual 1 of 4 Decoder/Demultiplexer February '85 Features CONNECTION DIAGRAM DIP TOP VIEW î. C IT « <? A,a C 0„a C 1 16 2 15 3 14 4 13 C 5 12 0 2a c 6 11 0 3a c 7 10 8 9 o„ GND C 3 v cc ^ Aob -I Alb -I Oob ^ o lb 3 o 2b TT O cr • High latch-up immunity

Contextual Info: ^ S u p e r te x in c . HCT139 HCT239 Octal Decoders/Dem ultiplexers Ordering Information Package Outputs Commercial 74HCT Military 54HCT Military Hi-Rel RB 54HCT N/A 16-pin plastic DIP Inverted Non-lnverted 74HCT139P 74HCT239P N/A 16-pin CERDIP Inverted Non-lnverted

74hc139

Contextual Info: 74HC139-Q100; 74HCT139-Q100 Dual 2-to-4 line decoder/demultiplexer Rev. 1 — 19 June 2014 Product data sheet 1. General description The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs nA0, nA1 to four mutually exclusive outputs (nY0 to nY3). Each decoder features an

PC 74HC139

Abstract: 74hc139
Contextual Info: G E SOLID STATE D1 Technical D a ta - DE~| 3075001 DGllSbl 3 ï D T “6>áj-ai-‘5'5" — . CD54/74HC139 CD54/74HCT139 File N u m b e r 1545 High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer AO 2 tl4 Typ e Features: • M ultifunction Capability

817n

Abstract: RJ10 33N3
Contextual Info: Si p € /i ' Corporata! ▼ SP8530 SIG N A L PR O C E S S IN G E X C EL LE N C E S2ADC - Simultaneous Sampling Analog to Digital Converter • ■ ■ ■ ■ ■ Simultaneous Sampling of 2 channels 12 Bit Resolution Single +5Volt Supply Internal Reference

MC68HC16Z1CFC16

Abstract: 10K SIP Resistor 3FW 94 lcd 2X20 RAM 62256 80C32MOD-ULE-DIP 3FW 59 80C32 MAX147EVC16-DIP MAX147EVC32-DIP
Contextual Info: 19-4751; Rev 1; 1/97 MAX147 Evaluation System/Evaluation Kit _Component List DESIGNATION QTY DESCRIPTION C1, C7–C14 9 0.01µF ceramic capacitors C2, C4, C6, C15, C17–C20 8 0.1µF ceramic capacitors C3 C5 C16 J1 J18 JU1, JU2, JU5 R1-R8

u574

Abstract: 74HCT7266 MXM 3 CONNECTOR 27C64 ROM crystal 11.059MHZ 1N4001 1N4148 1N5817 2N7000 74HCT138
Contextual Info: 19-0013; Rev 0; 3/92 EVALUATION KIT /i/i/ixiyi/i M A X 180 Evaluation K it Ordering Information PART TEMP. RANGE M AX180EVKIT 0 #C to +70"C BOARD TYPE I Plastic DIP-Through Hole | EV K it The MAX180 EV kit allows the user to select various MAX180 operating modes and perform conversions

74HC9046

Abstract: 74hc128 74HCT4050 74HC1284 74hct133 74HCT4049 74HC7014 74hc164 74HC192 74HC93
Contextual Info: INTEGRATED CIRCUITS Package information Supersedes data of 1999 Jul 09 File under Integrated Circuits, IC06 1999 Sep 22 Philips Semiconductors Package information PACKAGE INFORMATION PART NO DIP N SO (D) SSOP (DB) TSSOP (PW) PIN COUNT 74HCU04 27-1 108-1