74HCT02 Search Results

74hc02 specifications

Abstract: SCHS125A 74HC02
Contextual Info: [ /Title CD74H C02, CD74H CT02 /Subject (High Speed CMOS Logic Quad Two- CD54/74HC02, CD54/74HCT02 Data sheet acquired from Harris Semiconductor SCHS125A High Speed CMOS Logic Quad Two-Input NOR Gate March 1998 - Revised May 2000 Features Description • Buffered Inputs

74HC_HCT02

Abstract: NXP 74HC family characteristics 74HC02 74HC02P 74HCT02 74hc02n 74hc02 specifications
Contextual Info: 74HC02; 74HCT02 Quad 2-input NOR gate Rev. 4 — 4 September 2012 Product data sheet 1. General description The 74HC02; 74HCT02 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

74HC02

Abstract: 74HCT02 74HCT02D 74HC02D 74HC02DB 74HC02N 74HCT02DB 74HCT02N JESD22-A114E
Contextual Info: 74HC02; 74HCT02 Quad 2-input NOR gate Product data sheet 1. General description The 74HC02; 74HCT02 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL . The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74HCT02

Abstract: 74HC02 gd74hc02 74LS02 gate diagram GD54HC02 74HC 74LS02 pinout
Contextual Info: GD54/74HC02, GD54/74HCT02 QUAD 2-INPUT NOR GATES General Description These devices are identical in pinout to the 5 4 /7 4 L S 0 2 . T hey contain fou r in de pen de nt 2-input NOR gates. These devices are characteriz­ ed for operation over w ide tem perature ranges to

Contextual Info: Technical Data CD54/74HC02 CD54/74HCT02 File N um ber 1647 High-Speed CMOS Logic Quad 2-Input NOR Gate Type Features: • B uffered Inputs ■ Typical Propagation Delay = 7ns @ Vcc = 5 V, Cl= 15pF, r A = 25° C FUNCTIONAL DIAGRAM and TERMINAL ASSIGNMENT The RCA-CD54/74HC02 and CD54/74HCT02 logic gates

gd74hc02

Contextual Info: GD54/74HC02, GD54/74HCT02 QUAD 2-INPUT NOR GATES General Description These devices are identical in pinout to the 5 4 /7 4 L S 0 2 . T hey contain fou r in dep en de nt 2-input NOR gates. These devices are characteriz­ ed for operation over w ide tem perature ranges to

74HC02

Abstract: 74HCT02 74HCT02-Q100
Contextual Info: 74HC02-Q100; 74HCT02-Q100 Quad 2-input NOR gate Rev. 1 — 24 July 2012 Product data sheet 1. General description The 74HC02-Q100; 74HCT02-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL

Contextual Info: 74HC1G02-Q100; 74HCT1G02-Q100 2-input NOR gate Rev. 1 — 7 August 2012 Product data sheet 1. General description 74HC1G02-Q100 and 74HCT1G02-Q100 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The standard output currents are half those of the 74HC02-Q100 and 74HCT02-Q100.

74HC02

Contextual Info: 74HC02-Q100; 74HCT02-Q100 Quad 2-input NOR gate Rev. 1 — 24 July 2012 Product data sheet 1. General description The 74HC02-Q100; 74HCT02-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL

LM 4017 decade counter driver

Abstract: 74HC7244A 74HCT7007A 74HC11A 74HC85A 74HC147 decimal to binary encoder cmos 4008 74HC21A 74HC07A 74HC7244
Contextual Info: 2.H IG H SPEED CMOS SELECTION GUIDE NÄ N D NOR A ND OR IN V E R T E R ,B U F FE R 74HC00A 74HCT00A 74HC03A 74HC10A 74HC20A 74HC30 71HC132A 74HC133A GATE 74HC02A 74HCT02A 74HC27A 74HC4002A 74HC4078 74HC08A 74HCT08A 74HC09A 74HC11A 74HC21A 74HC32A 74HCT32A 74HC4072

74HCT02

Contextual Info: Technical Data CD54/74HC02 CD54/74HCT02 File Number 1647 T - H 3 'Z I 'CO High-Speed CMOS Logic S7E D HARRI S S E M I C O N D SE CT OR 4 3 0 2 27 1 001745*1 7 IHAS Quad 2-Input NOR Gate Type Features: • Buffered Inputs ■ Typical Propagation Delay - 7ns

54HCT02

Contextual Info: Technical Data CD54/74HC02 CD54/74HCT02 File N um b er 1647 High-Speed CMOS Logic Quad 2-Input NOR Gate Type Features: • Buffered Inputs ■ Typical Propagation Delay = 7ns @ V'cc = 5V, CL= 15pF, T„ = 25° C F U N C T IO N A L D IA G R A M and TER M IN A L A S S IG N M E N T

74HC02

Abstract: 74LS02 pin configuration 74LS02 pinout GD74HC02 74HCT02 74HC GD54HC32 GD74HCT02 GD74
Contextual Info: GD54/74HC02, GD54/74HCT02 QUAD 2-INPUT NOR GATES General Description Pin Configuration These devices are identical in pinout to the 54/74L S 02. They contain four independent 2-input NOR gates. These devices are characteriz­ ed for operation over wide temperature ranges to

74HCT02N PIN DIAGRAM

Abstract: 74HC02 74hc02 specifications 74HCT02 CMOS Quad 2-Input NOR Gate 74HC02,74HCT02 74HCT02D 74HCT02N 74HC02D 74HC02DB
Contextual Info: 74HC02; 74HCT02 Quad 2-input NOR gate Rev. 03 — 18 September 2008 Product data sheet 1. General description The 74HC02; 74HCT02 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

M74HCT02B1

Abstract: 74LS02 gate diagram 74LS02 74HCT02
Contextual Info: rz 7 SGS-Thomson M54H£I2? Ä 7 # û * M y i g r a K S M 74HCT02 QUAD 2-INPUT NOR GATE • HIGH SPEED tpD =11 ns (TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 nA (MAX.) AT Ta = 25 "C ■ COMPATIBLE WITH TTL OUTPUTS ViH = 2V (MIN.) ViL = 0.8V (MAX)

74HC02

Abstract: 74HCT02 74LV02 74LV02BQ 74LV02D 74LV02PW JESD22-A114E TSSOP14 DHVQFN14
Contextual Info: 74LV02 Quad 2-input NOR gate Rev. 04 — 20 December 2007 Product data sheet 1. General description The 74LV02 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC02 and 74HCT02. The 74LV02 provides a quad 2-input NOR function.

74HC02

Contextual Info: [ /Title CD74H C02, CD74H CT02 /Subject (High Speed CMOS Logic Quad Two- CD54/74HC02, CD54/74HCT02 Data sheet acquired from Harris Semiconductor SCHS125A High Speed CMOS Logic Quad Two-Input NOR Gate March 1998 - Revised May 2000 Features Description • Buffered Inputs

Contextual Info: 74HC02; 74HCT02 Quad 2-input NOR gate Rev. 4 — 4 September 2012 Product data sheet 1. General description The 74HC02; 74HCT02 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

74HC02

Abstract: 74HCT02 74HCT02D MM74HCT02N 74HC02N 74HCT02N 001aah768 74HC02D 74HC02DB 74HCT02DB
Contextual Info: 74HC02; 74HCT02 Quad 2-input NOR gate Product data sheet 1. General description The 74HC02; 74HCT02 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL . The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74LS02 gate diagram

Abstract: IC 74LS02 M54HCT02 M54HCT02F1R M74HCT02 M74HCT02B1R M74HCT02C1R M74HCT02M1R
Contextual Info: M54HCT02 74HCT02 QUAD 2-INPUT NOR GATE . . . . . . . HIGH SPEED tPD = 11 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

74HC9046

Abstract: 74hc128 74HCT4050 74HC1284 74hct133 74HCT4049 74HC7014 74hc164 74HC192 74HC93
Contextual Info: INTEGRATED CIRCUITS Package information Supersedes data of 1999 Jul 09 File under Integrated Circuits, IC06 1999 Sep 22 Philips Semiconductors Package information PACKAGE INFORMATION PART NO DIP N SO (D) SSOP (DB) TSSOP (PW) PIN COUNT 74HCU04 27-1 108-1

74LS02 gate diagram

Abstract: M54HCT02 M54HCT02F1R M74HCT02 M74HCT02B1R M74HCT02C1R M74HCT02M1R
Contextual Info: M54HCT02 74HCT02 QUAD 2-INPUT NOR GATE . . . . . . . HIGH SPEED tPD = 11 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

s134 p-mosfet

Abstract: 74hc260 Mitsumi D359T3 D359T3 schematic diagram inverter lcd monitor fujitsu 62256-10 BERG STRIP teac fd 235hf stepping motor mitsumi mitsumi floppy
Contextual Info: frt Page 1 Thursday, August 8, 1996 12:36 PM ÉlanSC300 Microcontroller Evaluation Board User’s Manual evalbd.book : frt Page 2 Thursday, August 8, 1996 12:14 PM ÉlanSC300 Microcontroller Evaluation Board, Revision 1.1 1996 by Advanced Micro Devices, Inc.

Mitsumi D359T3

Abstract: D359T3 Video Card AVED AV540 mitsumi floppy d359* mitsumi SCHEMATIC TRIDENT VGA board EPROM AMD s134 p-mosfet stepping motor mitsumi 62256-10
Contextual Info: evalbd.book : frt Page 1 Thursday, August 8, 1996 2:34 PM ÉlanSC310 Microcontroller Evaluation Board User’s Manual evalbd.book : frt Page 2 Thursday, August 8, 1996 2:34 PM ÉlanSC310 Microcontroller Evaluation Board, Revision 1.0 1996 by Advanced Micro Devices, Inc.