74167 COUNTER Search Results

Contextual Info: SN541G7, SN74167 SYNCHRONOUS DECADE RATE MULTIPLIERS DECEM BER 1972 - SN 54167. Perform Fixed-Rate or Variable-Rate Frequency Division SN 74167 . . . N PACKAGE T O P V IE W For Applications in Arithmetic. Radar, Digital-to-Analog (D/A), Analog-to-Digital

Contextual Info: NATIONAL SEMICOND {LOGIC} GEE D I b5D1155 DOLBflb? 3 I lb*7 I' T - Y ^ '0 7 CONNECTION DIAGRAM PINOUT A 54/74167 SYNCHRONOUS DECADE RATE MULTIPLIER nc 1 6 ]Vcc Ts] Si s3 T ÏT ] So ms |T 7ÏÏ1 MR 0z [ £ 12] Oy [ [ ]7 ]c l tc DESCRIPTION — The '167 contains a synchronous decade counter and four

TTL 74293

Abstract: 7490A TTL 7493A 74LS93 ttl 74LS173 74LS293 pin 74290 74293 74293 pin diagram 74LS293 Asynchronous counter
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D187 9397, 7497 D188 93167, 74167 0189 54LS/74LS173 9 10 14 15 k h 1 1 — 0 CE Ü 13 12 IE 9 - CP TC 1 0 — 0 Ez 1 2 - Gy 7 CP ;=3ID OE 1 ,1 5 - CPo 4 ,1 2 - C Pi MR Oo Q i Qz 03 2 ,1 4 5,11 3, 13

74167 counter

Abstract: 54167DM 54167FM 74167DC 74167FC 74167PC 74167 logic diagram 74167 decade counter
Contextual Info: 167 CO NNECTIO N DIAGRAM PINOUT A 54/74167 / / 3 ° ' SYNCHRONOUS DECADE RATE MULTIPLIER n c [T s2[T Tslsi s3[ I 141 So [7 T51 MR 5z [ | 12 ] Ey Oy [6 TT|ce t c [7 TÔ]Iz ms DESCRIPTION - The '167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub­

ttl 7497

Abstract: 74167 D196 D187 D188 D190 D194 D195 74167 logic diagram
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D187 9397, 7497 D188 93167, 74167 0189 54LS/74LS173 9 10 11 — 0 CE 14 15 k h Ü 13 12 IE 7 9 - CP 10—0 Ez 1 2 - Gy TC ;=3ID 1 ,1 5 - CPo 4 ,1 2 - C Pi MR Oo Q i Qz 03 2,14 5,11 7,9 3, 13 8, 10

types of binary multipliers

Abstract: SN74167 SN7497 1N3064 types of multiplication of binary multipliers
Contextual Info: TTL M SI C IR C U IT TYP ES SN7497, SN74167 S Y N C H R O N O U S R A T E M U L T IP L IER S SN7497 . . . 6-B IT B IN A R Y M U L T IP L IE R SN74167 . . . DECADE M U L T IP L IE R r 33 r-° Perform Fixed-Rate or Variable-Rate Frequency Division SN 7497 J O R N D U A L -IN -L IN E

74122

Abstract: 74LS568 TTL 74121 ttl 7497 54LS 96L02 96LS02 96S02 D187 D188
Contextual Info: FAIRCHILD DIGITAL TTL U p/D o w n 54LS 2,/74LS568 Presettable 16 L o g ic /C o n n e c tio n D ia g ra m Power D issipation s s J- _ _ _ D99 9Z 32 20 400 D187' 4L,7B,9B 32 20 325 D188 4L,7B,9B 54LS(2 /74LS569 3 Rate M u ltip lie r 54/7497 M.f./64 — 4 Rate M u ltip lie r

d4454

Abstract: TTL 74121 9602 Fairchild 74123 9602 74123 74122 74121 74123 Diagram TTL 74122 96L02
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL 040 9600 D41 9601 EXT R NC CAP Vcc Vcc EXT R NC CAP NC I L kl— Q Q E E E cD Lil 111LiJ 111 TD lil Lil Lil lirnj' Id NC GND D43 9603/74121 D42 9602, 96L02, 96S02, 96LS02 EXT vcc NC n cap NC NC EXT IN T R CAP R

74LS568

Abstract: TTL 74121 74167 74LSS02 74ls399 54LS 74LS266 9602 Fairchild 9602 74123 74ls379
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D93 54LS/74LS379 D94 9386, 74LS266, 54LS/74LS386 D95 54LS/74LS398 Vcc 1 4 5 12 13 4 5 7 6 14 15 17 16 lOa Ila lo b lib lo c lie lo d lid r ei f i r E5i r?i n S CP Qa Qb 2 GND Vcc = Pin 20 GND = Pin 10 Vcc = Pin 16

74167 logic diagram

Contextual Info: TYPES SN54167.SN74167 SYNCHRONOUS DECADE RATE MULTIPLIERS D E C E M B E R 1 9 7 2 -R E V IS E D DE CE M B E R 1983 • Perform Fixed-Rate or Variable-Rate Frequency Division • For A pplications in Arithmetic, Radar, Digital-to-Analog D/A , Analog-to-Digital

SN7497

Abstract: SN54167 SN5497 SN74167
Contextual Info: SN54167, SN741G7 SYNCHRONOUS DECADE RATE MULTIPLIERS SDLS064 DECEMBER 1 9 7 2 - S N 54167 . . . J OR W PACKAGE S N74167 , . . N PACKAGE Perform Fixed-Rate or Variable-Rate Frequency Division {TOP VIEW For Applications in Arithmetic, Radar, Digital-to-Analog D/A), Anaiog-to-Digital

Contextual Info: n i MSI TYPES SN541S7. SN741S7 SYNCHRONOUS DECADE RATE MULTIPLIERS B U L L E T IN NO D L-S 7211813. D E C E M B E R 1972 Perform Fixed-Rate or Variable-Rate Frequency Division SN54167 . . . J O R W PACKAGE SN74167 . . . J OR N PACKAGE For Applications in Arithmetic, Radar,

PHL 99 539

Contextual Info: SN54167, SN74167 SYNCHRONOUS DECADE RATE MULTIPLIERS DECEMBER 1 9 7 2 - REVISED M AR C H 1 9 8 8 S N 5 4 1 6 7 . . . J OR W P A C K A G E Perform Fixed-Rate or Variable-Rate Frequency Division SN74167 . . . N PACKAGE T O P V IE W For Applications in Arithmetic, Radar,

SN74115

Abstract: sn74l157 74S168 LST57 74L16 SN741157 SM74157 L-157
Contextual Info: TYPES SN54157. SN54L157, SNS4LSI57. SN54LS158. SN54S157, SN54S1S8. SN741S7, SN74L157, SN741S157, SH74LS158, SN74S1S7. SN74S158 QUADRUPLE 2-LINE-T0-1-LINE DATA SELECTORS/MULTIPLEXERS B U L L E T IN NO. DL-g 7711847. M ARCH 1 » 7 4 - R £ V I8 E P A U G U S T 1977

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 advantages for ic 7473 4 BIT COUNTER 74669 la 4508 ic schematic diagram XF107 74295 random number generator by using ic 4011 and 4017
Contextual Info: General Features The SCxD4 series of high performance CMOS gate arrays offers the user the ability to realise customised VLSI inte­ grated circuits featuring the speed performance previously obtainable only with bipolar technologies whilst retaining all the advantages of CMOS technology; low power consum p­

asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder MH 74151 counter 74169 74169 SYNCHRONOUS 4-BIT BINARY COUNTER
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T his series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder data sheet ic 74139 Quad 2 input nand gate cd 4093
Contextual Info: General Features The SCxD4 series of high perform ance CM O S gate arrays offers the user the ability to realise custom ised VLSI inte­ grated circuits featuring the speed perform ance previously obtainable only with bipo lar tech nolog ies whilst retaining all

DIN 72585

Contextual Info: 2014 Professional Quality Bits Complete Bits Program Toll Free: 800 494-6104 2 Terminator Impact Insert & Power Bit Sets High Performance Bits DESCRIPTION Page DESCRIPTION Page Terminator Impact Bits Slotted Dura Insert Bits 27 Phillips Dura Bits 27 4-5

priority encoder 74148

Abstract: priority encoder 74147 shift register 7495 msm7200 MSM7000 alu 74381 msm7500 MSM72000 74150 demultiplexer multiplexers 74 LS 150
Contextual Info: • G EN ER A L DESCRIPTION T h e M S M 7 0 0 0 0 series is the gate array L S I based on the master siice m ethod using the high perform ance silicon gate H C M O S process w ith the dual-layer metal structure. T h is series has the features to easily realize fu n c tio n s-o f the sch m itt trigger, crystal/

counter 74168

Abstract: 3-8 decoder 74138 counter 74169 Multiplexer 74152 74183 adder 74381 alu 74169 binary counter 74151 8 by 1 Multiplexer flip flop 74379 74175 flip flops
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T h is series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/

74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 jk flip flop to d flip flop conversion alu 74381 74541 buffer design excess 3 counter using 74161 two 3 to 8 decoders 74138 7444 series Excess-3-gray code to Decimal decoder
Contextual Info: • G E N E R A L D ESCRIPTIO N T h e M S M 7 0 H 0 0 0 series is the gate array L S I based on the m aster slice m ethod using the high perfo rm an ce silico n gate 2 m icro n H C M O S process w ith the d u al-layer m etal s tru ctu re . T h is series has the featu res to ea sily realize fu n c tio n s o f the sch m itt trig ger, c ry s ta l/

FZK101

Abstract: FZK105 upd101 SNF10 SN76131 TAA700 FZH111 FZJ101 MFC8010 MFC8001
Contextual Info: HANDBOOK OF INTESBATEI CIRCUITS in EQUIVALENTS AND SUBSTITUTES A lthough every care is taken with the preparation of this book, the publishers will not be responsible for any errors that might occur. I.S.B.N. 0 900162 35 X 1974 by Bernard B. Babani First Published 1974

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

PA0016

Abstract: STR11006 SO41P PIONEER PA0016 7 segment to bcd converter 74c915 SAJ141 74HC145 tms1122 IC PA0016 KOR 2310 transistor
Contextual Info: Utgåva 2005-03-24 Alla artiklar i katalogen finns normalt i lager men det tillkommer och utgår kontinuerligt. För aktuell information om prisvärt industriöverskott / surplus surfa in på: http://www.labb.se/surplus.htm Tel: 08-641 86 30 Fax: 08-641 87 30