64KX1 DRAM Search Results

KM416C60-7

Abstract: KM48C2104B KM416C60-6 KM48C2004B dram 64kx1 km416c60 KM44V1004CL-7
Contextual Info: General Information CMOS DRAM 1. Introduction j KM41C1000D-6 1M bit KM41C1000D-7 KM41C1000D-8 I KM41C1000D-L6|—¡ KM41C1000D-L7[— j KM41C1000D-L8 1 4M bit M 64Kx1« 4Mx1 KM48C124-55 —j KM48C124-6 KM48C124-7 KM416C60-55 — KM416C60-6 KM416C60-7 KM416C64-55

30A006-00

Abstract: 64KX1 dram 64kx1 64kx1 dram Dense-Pac Microsystems 2c195
Contextual Info: Dense-Pac Microsystems, Inc 64KX1 BASED . CM O S SRAM FAMILY - DIPS DESCRIPTION: The Dense-Pac 64KX 1 module family consists of very high speed 64K X 1 based static RAMs which have been con­ figured in the organizations described below. These modules are best suited for high speed military computers and

DPS320

Abstract: DPS384-25C a1528 DPS384 64KX1 dps320-45c
Contextual Info: DENSE-PAC n i C R OS YS TE dS D M D7E D | 275^415 □□□□□TD 64KX1 BASED e n se - P a c ic r o s y s t e m s , □ | In c . C M O S S R A M FA M IL Y •S IP S *7“- ^ - ¿ 3 - / Ô D ESCRIPTIO N : The Dense-Pac 64K X 1 module family consists of very high

DP5Z

Contextual Info: n INDEX GENERAL PRODUCT INFORMATION Dense-Pac Memory Module and Monolithic E merging T echnology / Products. Quality and R e lia b ilit y . Warranty . . 6 . 7 . 8 14 SRAM PRODUCTS

Block Diagram of 8057

Abstract: dram 64kx1 16kx4 64kx1 64kx1 dram IMS2600 IMS2620 Inmos Corporation Inmos inmos static ram
Contextual Info: IMS 2630 8Kx8 IMS 2620 16 Kx4 IMS 2600 6 4 K x1 Features Features Features • Byte wide 64K memory •C E access times of-120 and 150ns Cycle times of 190 and 240ns Non-multiplexed addressing On chip refresh counter for pin 1 hidden refresh 4ms, 256 cycle refresh

scn2692

Abstract: PAL Decoder 16L8 PHD48N22 SYSTEM GENERAL TURPRO-1 PHD48N22
Contextual Info: Philips Components-Signetics Programmable High-Speed Decoders PHD Application Note Programmable Logic Devices INTRODUCTION A recent Philips Com ponents-Signetics Application Note described how to perform microprocessor "High Speed Address Decode". This document

Contextual Info: MITSUBISHI <DIGITAL ASSP> M 66200A P/ AFP DRAM C O N T R O LLE R DESCRIPTION The M66200AP/AFP is a semiconductor integrated circuit for 256K- and 1M-bit CMOS-process DRAM controllers. The device can control all necessary DRAM signals, includ­ ing MPU, RAS and CAS memory control signals of signals

3524CP

Abstract: 2MX40 RAM128KX8 DIP HM624256 HM62832 16Mbit FRAM Dram 168 pin EDO 8Mx8 hm62256 flash 32 Pin PLCC 16mbit HN27C1024
Contextual Info: Memory Shortform, May '97 Memory Products Fast Page Mode DRAM DRAM EDO DRAM Synchronous DRAM SRAM Low Power SRAM Fast SRAM Non Volatile EPROM & OTPROM Memories EEPROM FRAM Fast Page Mode DRAM Modules EDO DRAM Modules SDRAM Modules FLASH Memory FLASH FLASH CARDS

Contextual Info: GE C P L E S S E Y S E M I C O N D U C T O R S | 2066-2.1 MV1815 SINGLE CHIP TELETEXT DECODER FOR 625 LINE OPERATION The MV1815 is an advanced CMOS single chip Teletext decoder for 625 line World System Teletext. The MV1815

sdc 7500

Abstract: ps sdc 7500 vdo rd3 serbo teletext sub-code dram 64kx1 W0017 001F8 SDS st2 MGC capacitor
Contextual Info: GEC PLESSEY S E M I C O N D U C T O R S | _ _ 2 0 6 6 - 2.1 MV1815 SINGLE CHIP TELETEXT DECODER FOR 625 LINE OPERATION The MV1815 is an advanced CMOS single chip Teletext decoder for 625 line World System Teletext. The MV1815

VL86C010

Abstract: VL86C110 27e transistor VL86C11010QC 13OO3 LPN12
Contextual Info: i L S I TECHNOLOGY INC S7E D • i3a&347 QQQblSb Ö ■ VLSI T e c h n o l o g y , in c . ' V 9 2 -3 3 - 2 1 VL86C110 RISC MEMORY CONTROLLER MEMC FEA TU RES DESCRIPTION • Drives up to 32 standard dynamic RAMs giving 4 Mbytes of real memory with 1-Mbit devices

TMS34061FNL

Abstract: lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625
Contextual Info: SM J 3 4 0 1 0 GRAPHICS SYSTEM PROCESSOR NOVEMBER 1 98 8 - • Military Temperature . . . - 5 5 ° C to 12 5°C • Instruction Cycle Time: 200 ns . . . S M J3 4010-40 160 ns . . . S M J3 4010-50 REVISED SEPTEMBER 1989 GB PACKAGE 68-PIN GRID ARRAY TOP VIEW

tms34061fnl

Abstract: TMS34070NL TMS34061FN TMS34061 TMS4464 TMS34010 SPVU001 Texas Instruments 34010 TMS34070 TMS4461
Contextual Info: TMS34010 GRAPHICS SYSTEM PROCESSOR o I^ o 004773 JA N U A R Y 1 9 8 6 - REVISED JULY 1 9 8 7 FN PACKAGE Instruction Cycle Time: - 16 0 ns . . . T M S 34 01 0-50 - 2 0 0 ns . . . (T M S 3 4 01 0-40) (TOP VIEW ) I il i l 9 Pixel Processing, XY Addressing, and

mcm2018a

Abstract: sun hold RAS 0610 cqq 765 RT IC HX 710B U256D
Contextual Info: Selector Guide and Cross Reference CMOS Dynamic RAMs DRAM Modules Video RAMs Pseudo Static RAMs General MOS Static RAMs CMOS Fast Static RAMs CMOS Fast Static RAM Modules Application Specific MOS Static RAMs MOS EEPROM Military Products Reliability Information

sun hold RAS 0610

Abstract: oki Logic Motorola transistor 7144 MSC2304 M5M41000
Contextual Info: Selector Guide and Cross Reference CMOS Dynamic RAMs DRAM Modules Video RAMs Pseudo Static RAMs General MOS Static RAMs CMOS Fast Static RAMs CMOS Fast Static RAM Modules Application Specific MOS Static RAMs MOS EEPROM Military Products Reliability Information

82c822

Abstract: la2 -d22 a65 82C206 opti viper
Contextual Info: • m P W rn V B r a r i n i iv a IIV J I I I I I ■ 82C546/82C547 Python Chipset 1.0 Features • 100% PC/AT compatible Supports 3-2-2-2 cache burst read cycles at 66M H z • Fully supports the 3.3V /5.0V Pentium processors Built-in tag auto-invalidation circuitry

M1L4

Contextual Info: 1 «*a V29BM C Burst Mode Memory Controller Data Sheet Features • Interfaces directly to Am 29000 Local C hannel • On C hip M em ory Address M ultiplexer/D rivers • M anages Page M ode D ynam ic M em ory devices • Flexible Instruction/D ata Bus B uffer M anagem ent

m6258

Abstract: transistor fst 239 MSM6258 ym22 SC2305 SC4M MSM6258VGSK B2N transistor
Contextual Info: O K I Semiconductor M SM 6258/M SM 6258V ADPCM SPEECH PROCESSOR FOR SOLID STATE RECORDER GENERAL DESCRIPTION T h e M S M 6258 is a com p lex and high ly in te­ g rated A D P C M sp e ech p ro ce sso r, im p le ­ m en ted in C M O S tech n o log y for low pow er

85C471 sis

Abstract: 85c407 85C471 SIS85C471 85C407 sis SIS 85C471 80486 ADDRESSING MODES cyrix 486 INTEL P24T Cyrix 486 dx2
Contextual Info: 85C471 Green PC ISA-YES A Single Chip 1. 85C471 OVERVIEW 1,1 Introduction The SiS85C471 single chip controller supports Intel's 80486DX2/DX/SX/SL Enhanced, P24D/P24T/P24C CPU, Cyrix's Cx486S2 M6/M7 CPU and AMD's Am486DXL/DXL2 CPU The SiS85C471 is a high performance, 100% PC/AT compatible single chip controller,

Cyrix 486

Abstract: 486DLC Cyrix 486 dx2 IBM Blue Lightning t418 opti 486 chipset dram 64kx1 82c499b1 isa bus master 386 82C499
Contextual Info: OPTi 82C499 DX System Controller Data Book Version 1.0 912-3000-001 August, 1994 Copyright Copyright 1994, OPTi Inc. ALL RIGHTS RESERVED. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of OPTi Inc.

PA0016

Abstract: STR11006 SO41P PIONEER PA0016 7 segment to bcd converter 74c915 SAJ141 74HC145 tms1122 IC PA0016 KOR 2310 transistor
Contextual Info: Utgåva 2005-03-24 Alla artiklar i katalogen finns normalt i lager men det tillkommer och utgår kontinuerligt. För aktuell information om prisvärt industriöverskott / surplus surfa in på: http://www.labb.se/surplus.htm Tel: 08-641 86 30 Fax: 08-641 87 30

Contextual Info: WD60C40A INTRODUCTION 1.0 INTRODUCTION 1.1 ARCHITECTURAL DESCRIPTION The WD60C40A peripheral cache manager PCM is a custom enhancem ent of the WD60C40, and is intended to be a drop-in re­ placement for the latter device. The WD60C40A is fully compatible with the WD60C40 as far as func­

029z3

Abstract: opti 82c206 82C822 MD2816 XA-495 LA2735 LA3155 opti 82C546 la2 -d22 a65 opti 82c547
Contextual Info: • m p m u n m m i !9.w m iiu mm ■■■ 82C546/82C547 Python Chipset 1.0 • Features Supports 3-2-2-2 cache burst read cycles at 66MHz 100% PC/AT compatible • Fully supports the 3.3V/5.0V Pentium processors Built-in tag auto-invalidation drcuitry

p54c

Abstract: SiS 85C503 85c501 3-8 decoder 74138 pin diagram 3-8 decoder 74138 85c503 9ROM SiS85C501 SiS chipset T54B
Contextual Info: Pentium/P54C PCI/ISA Chipset 1 85C501/502/503 Overview SiS85C501 SiS85C502 SiS85C503 PCI/ISA Cache Memory Controller PCMC PCI Local Data Buffer (PLDB) PCI System I/O (PSIO) A whole set of the SiS85C501, 85C502, and 85C503 provides fully integrated support for the