54LS73 Search Results

Contextual Info: M M O T O R O L A M ilita ry 54LS 73A Dual J-K Flip-Flop W ith C lear ELECTRICALLY TESTED PER: MIL-M-38510/30101 M P O /////// The 54LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs

Contextual Info: M MOTOROLA M ilitary 5 4 LS 7 3 A Dual J-K Flip-Flop With Clear ELECTRICALLY TESTED PER: MIL-M-38510/30101 The 54LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that w hen the clock goes HIGH, the inputs are enabled and data will be accepted. The logic of the J and K inputs may

7473 JK flip flop

Abstract: IC 74LS73 74LS73D 7473PC 74LS73 dual JK JK flip flop IC Flip-Flop 7473PC pin DIAGRAM OF IC 7473 74LS73 JK JK flip flop IC diagram
Contextual Info: 73 CO NNECTIO N DIAGRAM PINOUT A •A /Â 54/7473 ^ /54H /74H 73 O f1014 I/54LS/74LS73 DUAL JK FLIP-FLOP With Separate Clears and Clocks) D E S C R IP TIO N — The ’73 and ’H73 dual JK master/slave flip -flop s have a separate clock fo r each flip -flop . Inputs to the master section are controlled

J-K Flip flops

Abstract: LS73A LS73 SN5473 SN54LS73A SN74 SN7473 SN74LS73A
Contextual Info: SN5473, 54LS73A, SN7473, SN74LS73A □UAL J-K FLIP-FLOPS WITH CLEAR SDLS118 DECEMBER 1983 - • Package Options Include Plastic "Small Outline'' Packages. Flat Packages, and Plastic and Ceramic DIPs REVISED MARCH 1988 S N 5 4 7 3 . S N 5 4 L S 7 3 A . . . J OH W PA CK A G E

74s188 programming

Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
Contextual Info: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

54LS641

Abstract: CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623
Contextual Info: MAXIMUM RATINGS Supply Voltage - Vcc T h e S e rie s 5 4 L S /7 4 L S Schottky TTL family features both Schottky-barrier-diode inputs and em itte r inputs and u tilizes full Schottky-barrier-diode clamping to achieve speeds com parable to Series 54/74 at one-fifth of the

pin diagram for IC 7473

Abstract: pin DIAGRAM OF IC 7473 74LS73D pin diagram of 7473 7473PC ic 7473 pin diagram IC 7473 fan out 74ls73 IC 74LS73 74LS73 dual JK
Contextual Info: ' NATIONAL SENICOND {LOGIO DEE D | b S D l l S E OOfc.3712 7 | 73 r-¥ù-o7'0r CO N N ECTIO N DIAGRAM PIN O UT A 54/7473 54H/74H73 54LS/74LS73 DUAL JK FLIP-FLOP W ith S ep arate Clears and Clocks D ESC R IP TIO N — The ’73 and 'H73 dual J K master/slave flip-flops have a

54LS73A

Abstract: qml-38535 CDFP2-F14 GDFP1-F14
Contextual Info: REVISIONS DATE YR-MO-DA DESCRIPTION LTR APPROVED REV SHEET REV SHEET REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REV SHEET 8 PREPARED BY

LG color tv Circuit Diagram schematics

Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
Contextual Info: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

Contextual Info: M MOTOROLA M ilita ry 54L S 73A Dual J-K Flip-Flop W ith C lear ELECTRICALLY TESTED PER: MIL-M-38510/30101 M mini The 5 4 L S 7 3 A offers individual J, K, clear, and clock inputs. These dual flip -flo p s are desig n ed so th a t w hen the clo ck g oe s HIG H , th e inputs

ay-5-1012

Abstract: ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor
Contextual Info: GENERAL INFORMATION lie of Contents • Alphanumeric Index • Selection Guides • Glossary INTERCHANGEABiliTY GUIDE MOS MEMORIES TTL MEMORIES ECl MEMORIES MICROPROCESSOR SUMMARY 38510/MACH IV PROCUREMENT SPECIFICATION JAN Mll-M-38510 INTEGRATED CIRCUITS

pin diagram for IC 7473

Abstract: 7473PC ic 7473 pin diagram of 7473 pin DIAGRAM OF IC 7473 7473 pin diagram Flip-Flop 7473PC 74LS73 dual JK IC 74LS73 74LS73DC
Contextual Info: 73 CONNECTION DIAGRAM PIN O U T A 54/7473 ^ , 54H /74H 73 o/IOti/ 1/54LS/74LS73 &/ / i ’ /3 DUAL JK FLIP-FLOP With Separate Clears and Clocks DESCRIPTION — The ’73 and ’H73 dual J K master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled

74LS73AN

Abstract: Q356
Contextual Info: R C H U - P S E M IC O N D U C T O R tm DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs sition tim e of th e negative going edge o f the clock pulse. The data on the J and K inputs is allowed to change w hile the

Contextual Info: TYPES SN5473, SN54H73, SN54L73, 54LS73A, SN7473, SN74H73, SN74LS73A DUAL J- K FLIP-FLO PS WITH CLEAR E V IS E D D E C E M B E R 1 9 8 3 • * Package Options Include Plastic and ■ Ceramic DIPs

2650B

Abstract: wf vqc 10d alu 9308 d Signetics 2650 SN52723 2650 cpu 82S103 pipbug Signetics NE561 cd 75232
Contextual Info: flcnCTICf ßii>ouiR/mos fflICROPROCEÍSOR DATfl mnnuni SIGNETICS reserves the right to make changes in the products contained in this book in order to improve design or performance and to supply the best possible products. Signetics also assumes no responsibility for the

54LS73

Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 04/11/98 Last Update Date: 08/24/98 Last Major Revision Date: 04/11/98 54LS73-X REV 0A0 DUAL NEGATIVE EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS with CLEAR and COMPLIMENTARY OUTPUTS General Description This device contains two independent negative-edge triggered J-K flip-flops with

54l73

Abstract: IC TTL 7473 SN54L73 IC 7473
Contextual Info: TYPES SN5473, SN54H73, SN54L73, 54LS73A, SN7473, SN74H73, SN74LS73A DUAL J-K FLIP-FLOPS WITH CLEAR REVISED DECEMBER 1983 Package Options Include Plastic and C eram ic DIPs S N 5 4 L 7 3 . , . J P AC KA G E S N 7 4 7 3 , S N 7 4 H 7 3 . . . J OR N P AC K A G E

54LS73A

Contextual Info: S E M IC O N D U C T O R TM DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs sition tim e of th e negative going edge o f the clock pulse. The data on the J and K inputs is allowed to change w hile the

sn55470

Abstract: 7544-1 transistor SN75326 SN7401 SN75426 54175 SN75270 SN55450 sn75493 National Semiconductor Linear Data Book
Contextual Info: The Interface Circuits Data Book for Design Engineers First Edition IM P O R T A N T NO TICES Texas Instruments reserves the right to make changes at any tim e in order to im prove design and to supply the best product possible. T l cannot assume any responsibility for any circuits shown or