54LS54 Search Results

.5J1

Abstract: 54LS54DMQB 54LS54FMQB DM74LS54M DM74LS54N J14A M14A N14A W14B
Contextual Info: LS54 2 3 National Semiconductor 54LS54/DM74LS54 4-WIDE, 2-Input AND-OR-INVERT Gate General Description This device contains a combination of four, two input AND gates whose outputs are connected to a four input NOR Gate. Connection Diagram Dual-ln-Line Package

LS540

Abstract: LS-541 LS541 SN54LS240 SN54LS540 SN54LS541 SN74LS240 SN74LS540 SN74LS541 d2e4
Contextual Info: 54LS540, 54LS541, SN74LS540, SN74LS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3 STATE OUTPUTS SDLS180 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers D 2 E 4 6 , A U G U S T 19 7 9 -F IE V IS E D M AR CH 198 8 S N 54LS 540, SN 54LS541 . J OR W PA CK AG E

54LS540

Contextual Info: T Y P E S 54LS540, 54LS541, SN74LS540, SN74LS541, O C T A L B U F F E R S A N D LIN E D RIVERS WITH 3 -S T A T E O U TPU TS D 2 5 4 6 , A U G U S T 19 7 9 - R E V I S E D A PR IL 1 9 8 5 3-State O u tp u ts D rive Bus Lines or SN 54LS540, SN 54LS541 . J P A C K A G E

Contextual Info: NATIONAL SEMICOND -CLOGÏO 31E D bSOllSa QQbTôD3 7 National Semiconductor / - v 3- 16-00 54LS54/DM74LS54 4-WIDE, 2-lnput AND-OR-INVERT Gate General Description This device contains a combination of four, two Input AND gates whose outputs are connected to a four Input NOR

Contextual Info: MOTOROLA Military 54LS54 4-Wide 3-2-2-3 Input AND/OR/INVERT Gate ELECTRICALLY TESTED PER: MIL-M-38510/30402 AVAILABLE A S : LOGIC DIAGRAM Vcc 1 JAN : JM38510/30402BXA NC 2) SM O: * 3) 883C: 54LS54/BXAJC X = C A S E OUTLINE A S FO LLOW S: PACKAGE: CERDIP: C

DM74LS

Contextual Info: LS54 yw\National ÆÜSemiconductor 54LS54/DM74LS54 4-WIDE, 2-Input AND-OR-INVERT Gate General Description This device contains a combination of four, two input AND gates whose outputs are connected to a four input NOR Gate. Connection Diagram Dual-ln-Line Package

74LS PINOUT

Abstract: 74H54FC 74LS54PC 7454DC 7454FC 7454PC 74H54DC 74H54PC 74LS54DC 74LS54FC
Contextual Info: 54 C O N N E C T IO N D IA G R A M S P IN O U T A Vm /7454 ^54H/74H54^ 54LS/74LS54 ^ 4-W IDE, 2-IN PU T AND-O R -IN VER T GATE O R D E R IN G CO D E: See S e c tio n 9 PIN PKGS P la stic D IP P C O M M E R C IA L GRADE M IL IT A R Y G RADE V cc = +5.0 V ±5%,

Sn 7464

Abstract: TTL 7464
Contextual Info: TYPES SN5454, SN54H54, SN54L54, 54LS54, SN7454, SN74H54, SN74LS54 4-WIDE AND-OR-INVERT GATES R E V I S E D D E C E M B E R 19B3 Package Options Include Both Plastic and Ceram ic Chip Carriers In Addition to Plastic and Ceramic DIPs SN 5464 . . . J P A C K A G E

triac zd 607

Abstract: 1n5204 CA2820 TRW 2N4427 equivalent bfr91 2N6823 842 317 SO8 BD243 PINOUT BD529 bf506 BF845
Contextual Info: MASTER SELECTION GUIDE EUROPEAN SUPPLEMENT This is the European supplement to the USA edition of the Master Selection Guide, SG73/D REV 3. It should be read along with the USA edition. The supplement carries amendments to sections 1 and 5 in the USA edition.

74s188 programming

Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
Contextual Info: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

Contextual Info: SN5454, 54LS54, SN7454, SN74LS54 4-WIDE AND OR INVERT GATES D EC EM BE R 1 9 8 3 -R E V IS E D M A R C H • • SN54S4 JPACKAGE SN7454 . . . N PACKAGE Package Options Include Plastic "Sm all O utline" Packages. Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

75115

Abstract: 74LS540DC 75 LS541 54ls541 74LS540PC LS-541 74LS541 54LS540DM 74LS540FC 74LS541PC
Contextual Info: 540 • 541 C O N N E C T IO N D IA G R A M S P IN O U T A Ì4LS /74LS 540 5 4 L S /7 4 L S 5 4 1 «'Vôfe«? O C TAL BUFFER/LINE DRIVER (W ith 3-State O utputs D E S C R IP T IO N — T he ’LS540 an d ’LS541 are s im ila r in fu n c tio n to th e 'LS240

74LS54PC

Abstract: V745 74LS5 74H54DC
Contextual Info: 54 CO NNECTIO N DIAGRAMS PINOUT A VÌ4/7454 ' S4H/74H54 ' 54LS/74LS54 ¿-j- <7 oo r v 4-WIDE, 2-INPUT AND-OR-INVERT GATE ORDERING CODE: See Section 9 PIN PKGS Plastic DIP P COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0 ° C to +70° C Vcc = +5.0 V ±10%,

75 LS541

Abstract: 74LS540DC 74LS540PC
Contextual Info: 540 • 541 CO NNECTION DIAGRAMS PINOUT A r / c U ? ' ¡4LS/74LS540 i^4LS/74LS541 ^ f b ( o 9 % OCTAL BUFFER/LINE DRIVER (W ith 3 -S tate Outputs DESCRIPTION — The ’LS540and ’LS541 are sim ilar in function to the 'LS240 and ’LS241, respectively, except that the inputs and outputs are on opposite

LG color tv Circuit Diagram schematics

Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
Contextual Info: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS

54S38

Abstract: SN74298 SN74265 54175 NES 1004 naval specification 74L95 Transistor AF 138 07802-1 SN7437 SN54LS195A
Contextual Info: m - G EN ER A L IN F O R M A TIO N INDEXES Numerical • Functional/Selection Guide O R D E R IN G INSTRUCTIO NS A N D M E C H A N IC A L D ATA 1 1 5 4/74 F A M IL Y SSI C IR CU ITS 2 I 54/74 F A M IL Y M S I/LSI C IR C U ITS 3 S E R IE S 29000 S S I C IR C U IT S

54LS540

Contextual Info: REVISIONS LTR B C D E S C R IP T IO N Change tpnz- Change to military drawing format. Case S inactive for new desiqn. Change tpnz- Add footnote for propagation delay times. Change C|_. Add R package with footnote change to Vq h I f°r Vj|_. DATE 19 Marci 1987

CI 7454

Abstract: CI 74ls54 7454 74H54 74H 14 N7454F N7454N N74H54F N74H54N N74LS54F
Contextual Info: PIN CONFIGURATIONS 5 4 /7 4 5 4 54H /74H 54 54LS/74LS54 ORDERING CODE S ee Section 9 fo r further P ack ag e and Ordering Inform ation COMMERCIAL RANGES MILITARY RANGES VC C = 5V ± 5% ; T a = 0"C to + 7 0 °C VC C = 5 V ± 10% ; TA= —55°C to + 1 2 5 X

ay-5-1012

Abstract: ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor
Contextual Info: GENERAL INFORMATION lie of Contents • Alphanumeric Index • Selection Guides • Glossary INTERCHANGEABiliTY GUIDE MOS MEMORIES TTL MEMORIES ECl MEMORIES MICROPROCESSOR SUMMARY 38510/MACH IV PROCUREMENT SPECIFICATION JAN Mll-M-38510 INTEGRATED CIRCUITS

74LS54PC

Abstract: 74H54
Contextual Info: NATIONAL SEniCOND {LOGICI 02E D | t.501122 D-DbabTS □ I T "/S' 54 CO NN ECTIO N DIAGRAM S PINOUT A 54/7454 54H/74H54 54LS/74LS54 4-WIDE, 2-INPUT AND-OR-INVERT GATE ORDERING CODE: See S ection 9 PIN PKGS Plastic DIP P C eram ic DIP (D) Flatpak (F) O UT