54LS112 Search Results

Contextual Info: SN 54LS112A , S N 54S 112, SN 74LS112A , S N 74S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS W ITH PRESET AND CLEAR D 2 6 6 1 . APRIL 1 9 8 2 - REVISED M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance r a a SN 54LS 112A , SN 54S 112 . . . J OR W PACKAGE

dm74 Series

Abstract: 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM
Contextual Info: LS112A National Semiconductor 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

Contextual Info: LS112A National Semiconductor 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

CP12A-1

Contextual Info: M MOTOROLA M ilitary 54LS112A D u a l J -K Flip-Flop W ith C le a r an d Pre se t ELECTRICALLY TESTED PER: MIL-M-38510/30103 The 54LS112A dual flip-flop features individual J, K, clock, and asyn­ chronous set and clear inputs to each flip-flop. When the clock goes

Contextual Info: & > M ilitary 54LS112A MOTOROLA Dual J -K Flip-Flop W ith C lear and P reset lllllll ELECTRICALLY TESTED PER: MIL-M-38510/30103 M PO The 54LS112A dual flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes

dm74ls112an

Abstract: 54LS112 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112A DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM
Contextual Info: 54LS112 54LS112A DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and

Contextual Info: & June 1989 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

O406

Abstract: 54LS112 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112AM DM74LS112AN E20A
Contextual Info: June 1989 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

54LS112

Contextual Info: M MOTOROLA M ilitary 54LS112A Dual J -K Flip-Flop W ith C lear and P reset MPO lllflll ELECTRICALLY TESTED PER: MIL-M-38510/30103 The 54LS112A dual flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes

74LS112AN

Abstract: 74LS112AM
Contextual Info: I R C H I L D S E M I C O N D U C T O R TM DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains tw o independent negative-edge-triggered J-K flip-flops w ith com plem entary

54LS112

Abstract: 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM DM74LS112AN E20A
Contextual Info: S E M IC O N D U C T O R tm DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains tw o independent negative-edge-triggered J-K flip-flops w ith com plem entary

74s188 programming

Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
Contextual Info: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

54LS641

Abstract: CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623
Contextual Info: MAXIMUM RATINGS Supply Voltage - Vcc T h e S e rie s 5 4 L S /7 4 L S Schottky TTL family features both Schottky-barrier-diode inputs and em itte r inputs and u tilizes full Schottky-barrier-diode clamping to achieve speeds com parable to Series 54/74 at one-fifth of the

54s112

Abstract: 74LS112A 74S112
Contextual Info: 54LS112A, SN54S112, SN74LS112A. SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR _ Fully Buffered to Offer Maximum Isolation from External Disturbance • D 2 6 6 1 . A P R IL 1 9 8 2 - R E V I S E D M A R C H 1 9 8 8

LG color tv Circuit Diagram schematics

Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
Contextual Info: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS

Contextual Info: 112 CONNECTION DIAGRAM P IN O U T A 54S/74S112 t1" 00 \/&4LS/74LS112 b DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The '112 features individual J, K, C lo ck and asynchronous Set and C lear inputs to each flip-flop. When the clo ck goes HIGH, the inputs

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

LS112A

Abstract: SN54LS112 SN54LS112A SN54S112 SN74 SN74LS112A SN74S112A
Contextual Info: SN5 4 L S 112A, SN5 4 S 112, SN7 4 L S 112A, SN7 4 S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR D 2 6 6 1 . A P R IL 1 9 8 2 - R E V IS E D M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 1 1 2 A . S N 5 4 S 1 1 2 . . . J OR W P A C K A G E

ay-5-1012

Abstract: ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor
Contextual Info: GENERAL INFORMATION lie of Contents • Alphanumeric Index • Selection Guides • Glossary INTERCHANGEABiliTY GUIDE MOS MEMORIES TTL MEMORIES ECl MEMORIES MICROPROCESSOR SUMMARY 38510/MACH IV PROCUREMENT SPECIFICATION JAN Mll-M-38510 INTEGRATED CIRCUITS

m38510/06301

Abstract: M38510-06302 m38510 m38510/20702 M38510/00801 M38510/00104 m38510/01201 M38510/20802 82S62 M38510/01302
Contextual Info: JAN/SMD Devices JAN/SMD Source JAN/SMD Source JAN/SMD Source M38510/00101 5430 M38510/07701 54S138 M38510/31512 54LS163A M38510/00102 5420 M38510/07702 54S139 M38510/31601 54LS75 M38510/00103 5410 M38510/07801 54S181 M38510/31603 54LS259 M38510/00104 5400

Contextual Info: R C H U - P S E M IC O N D U C T O R tm DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary