512X512X16 Search Results

Contextual Info: IB M 0 1 5 1 6 0 IB M 0 1 5 1 6 1 256K X 16 DRAM Features • 256K X • 66MHz EDO performance 16 DRAM • Non-Persistent WPBM mode • Performance: Parameter -40 -50 -60 tRP RE Precharge 20ns 25ns 30ns tCAC Access Time from CË 12ns 14ns 15ns Ua Column Address Access

MSM5416283-60

Abstract: MSM5416283 SAM256
Contextual Info: O KI Semiconductor MSM5416283 262,144-Word x 16-Bit Multiport DRAM DESCRIPTION The MSM5416283 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and asynchronously.

MSM5416283

Abstract: FJDS5416283
Contextual Info: お客様各位 資料中の「沖電気」「ＯＫＩ」等名称の OKI セミコンダクタ株式会社への変更について 2008 年 10 月 1 日を以って沖電気工業株式会社の半導体事業は OKI セミコン ダクタ株式会社に承継されました。 従いまして、本資料中には「沖電気工業株

SP126

Abstract: lg lcd tv panel circuit diagram free SPC8106F0B SPC8108FOC 4X12 lcd SP-1108 sp1 1r4 FL400 xe p001 XCSL
Contextual Info: S-MOS S Y S T E M S A Seiko Epson Affiliate SPC8106 LCD/CRT VGA CONTROLLER Data Sheet Copyright 1997 S-MOS Systems Inc. All rights reserved. VDC This document, and any text derived, extracted or transmitted from it, is the sole property of S-MOS Systems Inc. and may not be used, copied,

Contextual Info: OKI Sem iconductor MSM5416273 P relim inary 262,144 -Word x 16 Bits Multiport DRAM_ Rev.t.o GENERAL DESCRIPTION* The MSM5416273 is a 4-Mbit CMOS m ultiport DRAM composed of a 262,144-word by 16-bit dynamic RAM and a 512-words by 16-bits SAM. Its RAM and SAM operate independently and

Contextual Info: EPSON PF765-02 _ SPC8104F Low Voltage VGA LCD Controller • DESCRIPTION The SPC8104 is a low power, mixed voltage video controller based on VGA architecture and optimized for driving a 640x480 LCD panel display. VGA standard mode functionality is supported using standard IBM VGA

Contextual Info: O KI Semiconductor MSM5416283 262,144-Word x 16-Bit Multiport DRAM DESCRIPTION The MSM5416283 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and asynchronously.

Contextual Info: HY63V16400A 256Kx16bit CMOS FAST SRAM Preliminary DESCRIPTION FEATURES The HY63V16400A is a 4,194,304-bit high-speed SRAM organized as 262,144 words by 16 bits. The HY63V16400A uses sixteen common input and output lines and has an output enable pin which operates faster than address access time at

Contextual Info: $6/&.  9.ð&026'5$0 ('2 HDWXUHV • Organization: 262,144 words x 16 bits • High speed - 35/45/60 ns RAS access time - 17/20/25 ns column address access time - 7/10/10 ns CAS access time • Low power consumption - Active: 280 mW max (AS4LC256K16E0-35)

WM1-DIN

Abstract: MSM54V1627360
Contextual Info: J2L0025-17-Y1 作成：1998年 1月 MSM54V16273 l 前回作成：1997年 9月 ¡ 電子デバイス MSM54V16273 262,144-Wordx16-Bit MULTIPORT DRAM n 概要 ）ポー

Contextual Info: J2L0021-17-Y1 作成：1998年 1月 MSM5416273 l 前回作成：1997年 9月 ¡ 電子デバイス MSM5416273 262,144-Wordx16-Bit MULTIPORT DRAM n 概要 ）ポー

sub-micro CMOS technology

Contextual Info: VG26 V S4260D 262,144 x 16 - Bit CMOS Dynamic RAM VIS Description The device is CMOS Dynamic RAM organized as 262, 144-word x 16 bits. It is fabricated with an advanced submicro CMOS technology and advanced CMOS circuit design technologies. Fast Page Mode allows 512 random

Contextual Info: •HYUNDAI H Y 5 2 1 6 2 5 7 S e r ie s 256K X 16-bit Video RAM with 2WE Introduction O verview The 4megabit Video RAM is an application specific memory device designed for graphics applications. It comprises a 256k x16 DRAM memory array interfaced to a 256 x16 Serial Access Memory SAM , or register.

256x16* STATIC RAM

Contextual Info: O K I Semiconductor MSM54V16283 262,144-Word x 16-Bit Multiport DRAM DESCRIPTION The MSM54V16283 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and asy nchronously.

VG26426

Contextual Info: VG264260CJ 262,144 x 16 - Bit CMOS Dynamic RAM VIS Description The device is CMOS Dynamic RAM organized as 262, 144-word x 16 bits. It is fabricated with an advanced submicron CMOS technology and advanced CMOS circuit design technologies. It is packaged in

MSM54V16283

Contextual Info: FJDS54V16283-05 作成：2000年 2月 ¡ 電子デバイス 前回作成：1998年 1月 MSM54V16283 262,144-Wordx16-Bit MULTIPORT DRAM n 概要 ）ポー

FJDS5416283

Abstract: MSM5416283
Contextual Info: FJDS5416283-05 作成：2000年 2月 ¡ 電子デバイス 前回作成：1998年 1月 MSM5416283 262,144-Wordx16-Bit MULTIPORT DRAM n 概要 ）ポー

8I04

Contextual Info: S-MOS S Y S T E M S A Seiko E pson A ffilia te SPC8104F0A VGA LCD Controller Hardware Functional Specification Drawing Office No. X15-SP-001-08 C o p y r ig h t 1994, 1996 S -M O S S y s te m s Inc. A ll rig h ts re se rve d . T h is do c u m e n t, an d a n y te x t d e rived, ex tra c te d or tra n sm itte d from it, is the so le p ro p e rty o f S -M O S S y s te m s Inc. and m a y not be used, copied,

TC51V4265

Abstract: d2539
Contextual Info: TOSHIBA TC51V4265DFIS60/70 PRELIMINARY 262,144 WORD X 16 BIT DYNAMIC RAM Description TheTC51V4265DFTS is the new generation dynamic RAM organized 262,144 word by 16 bits. TheTC51V4265DFTS uti­ lizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating mar­

D482445LGW-A70

Abstract: cwi 1011
Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT /¿PD482444, 482445 4M-Bit Dual Port Graphics Buffer 256K-WORD BY 16-BIT D escrip tio n The /iPD482444 and ^PD482445 have a random access port and a serial access port. The random access port has a 4M-bit 262, 144 words x 16 bits memory cell array structure. The serial access port can perform clock

AS4LC256K16EO

Abstract: AS4LC256K16EO-35 AS4LC256K16E0-35JC RAS-28
Contextual Info: AS4LC256K16EO 3.3V 256K X 16 CMOS DRAM EDO Features • EDO page mode • 5V I/O tolerant • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words x 16 bits • High speed - 45/60 ns RAS access time - 10/12/15/20 ns column address access time

AS4C256K16FO

Abstract: AS4C256K16FO-60
Contextual Info: AS4C256K16FO 5V 256K X 16 CMOS DRAM Fast Page Mode Features • Organization: 262,144 words x 16 bits • High speed - 25/30/35/50 ns RAS access time - 12/16/18/25 ns column address access time - 7/10/10/10 ns CAS access time • Low power consumption

lcd ibm pinout

Abstract: 24CO2 30 Pinout panel lcd MD14 SPC8104 256K 4bit DRAM 256KDRAM
Contextual Info: PF765-02 SPC8104F Low Voltage VGA LCD Controller • DESCRIPTION The SPC8104 is a low power, mixed voltage video controller based on VGA architecture and optimized for driving a 640x480 LCD panel display. VGA standard mode functionality is supported using standard IBM VGA

UPD424260LE-70

Abstract: 512X512X16
Contextual Info: UPD424260LE-70 1/2 IL08 * C-MOS 4M (262,144x16) BIT DYNAMIC RAM - TOP VIEW - 1 V DD (+5V) GND 40 I/O1 IN/OUT 2 39 I/O16 IN/OUT I/O2 IN/OUT 3 38 I/O15 IN/OUT I/O3 IN/OUT 4 37 I/O14 IN/OUT I/O4 IN/OUT 5 36 I/O13 IN/OUT 6 V DD (+5V) GND 35 I/O5 IN/OUT 7