50PIA Search Results

Contextual Info: HM-65162 33 HARRIS 2048 x 8 Asynchronous CMOS Static RAM Features Pinouts DIP • Fast Access T im e . 55 /7 0 /9 0 n s M ax. • Low Standby C u rre n t. TO P VIEW 50piA M ax.

Contextual Info: r r i m LTC1426 m TECHNOLOGY Micropower Dual 6-Bit PWM DAC F€OTUR€S D€SCRIPTIOn • Wide Supply Range: 2.7V < V^c ^ 5.5V ■ Wide Reference Voltage Range: OV to 5.5V The LTC 1426 is a dual micropower 6-bit PWM DAC featuring versatile PWM outputs and aflexible pushbutton

Contextual Info: w GEC PLESSEY ADVANCE INFORMATION S E M I C O N D U C T O R S D.S. 3931 1.5 SP5654 2.7GHz 3-WIRE BUS CONTROLLED SYNTHESISER The SP5654 is a single chip frequency synthesiser designed for satellite TV tuning systems. It is a programming variant of the SP5655 allowing the design of one tuner with

Contextual Info: 74LS260, S260 Signetics Gates Dual 5-Input NOR Gate Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 74LS260 9ns 4 mA 74S260 4ns 22mA FUNCTION TABLE OUTPUT INPUTS A B c E Y H X X X X L X H X X X L X X H X X

IC 74175

Abstract: pin diagram of ic 74175 74ls175 pin diagram 74175 DIP ic 74175 pin diagram quad D flip-flop 74175 pin D flip-flop 74175 pin pin configuration 74175 N74LS175D 74ls175
Contextual Info: 74175, LS175, S 175 Flip-Flops S ig n e lic s Quad D Flip-Flop Product Specification Logic Products FEATURES • Four edge-triggered D flip-flops • Three speed-power ranges available • Buffered common clock • Buffered, asynchronous Master Reset TYPE

2N5326

Abstract: OTC2220 OTC2420 SVT60-5 SVT80-5
Contextual Info: OPTEK TE CH N O L O G Y INC 4flE D • bV T& Sa D □□G13ût. SST ■ OTK Product Bulletin OTC2420 August 1990 High Speed NPN Switching Transistor Die Type OTC242Q 80V, 5A Applications • Low Voltage Inverters • Pulse Amplifiers • Base Drive Circuits

Contextual Info: MX23C1B10 1 6 M -B IT T aM x 8 / 1 M X I B ] CM O S M A SK ROM FEATURES • • • • • Switchable configuration - 2M x 8 byte mode - 1 M x 16(word mode) • Single +5V power supply • Fast access time: 100/120/150/200ns (max) • Totally static operation

Contextual Info: CMOS MASK ROM KM23C8100A 8M-Bit 1M X 8 /5 1 2 K X 16 CMOS MASK ROM FEATURES GENERAL DESCRIPTION • S w itc h a b le o rg a n iz a tio n The KM23C8100A is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 1 ,0 4 8 ,5 7 6 X 8 bit

74ls112 pin diagram

Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
Contextual Info: 7 4 LS1 1 2 , S 1 1 2 Flip-Flops S ig n e t ic s Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and_Reset inputs. The Set So and Reset (R d) inputs, when LOW,

7L Marking

Contextual Info: LT1579 300mA Dual Input Smart Battery Backup Regulator F€flTUR€S D€SCRIPTIOfl • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LT 1579 is a dual input, single output, low dropout regulator. This device is designed to provide an uninterruptible output voltagefrom two independent input

SVT60-5

Abstract: 2N5326 OTC2220 OTC2420 OTC242Q svt80 SVT60
Contextual Info: b7^asaa 4flE D OPTEK TECHNOLOGY INC oaoiBfit, I OTK sst ü g jjU H b K Product Bulletin OTC2420 August 1990 " T Z G - »«1 High Speed NPN Switching Transistor Die Type OTC242Q 80V, 5A Applications • Low Voltage Inverters • Pulse Amplifiers • Base Drive Circuits

km681000clg-7l

Abstract: KM681000CLP-7 KM681000CLT-5L KM681000CLP-7L KM681000CLG KM681000C
Contextual Info: KM681000C Family CMOS SRAM 128K x8 bit Low Power CMOS Static RAM FEATURES G ENERAL DESCRIPTION • Process Technology: Q.4ftm C M O S • Organization: 128Kx8 • Power Supply Voltage : Single 5.0V±1Q% • Low Data Retention Voltage : 2V Mln • three state output and TTL Compatible

BIPD

Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT / ffP P 4264165, 4265165 64 M-BIT DYNAMIC RAM 4 M-WORD BY 16-BIT, HYPER PAQE MODE EDO , BYTE READ/WRITE MODE D escription The /iPD4264165,4265165 are 4,194,304 words by 16 bits CMOS dynamic RAMs with optional hyper page mode