29C94 Search Results

DM 311 BG 40

Abstract: DM 311 BG 42 K/DM 311 BG 29 DM 311 BG 30
Contextual Info: Tem ic 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description T he MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support im plem entation of high speed data links based on

ITR17

Abstract: ITR24 80X86 AD10 AD11 AD12 AD14 ITR28
Contextual Info: 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description The MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or

ITR30

Abstract: 0804H
Contextual Info: Tem ic 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description The MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of high speed data links based on

29C94

Abstract: ANM036 line E1 e1-t1
Contextual Info: ANM036 MATRA MHS Connecting 29C96 and 29C94 Introduction The 29C94 and 29C96 are parts of MHS's ISDN primary rate chipset. The 29C94 is a multichannel HDLC controller and the 29C96 is a framer with time slots switching capabilities. These two components can be used in T1-DS1 1.544MHz or E1-CEPT

ITR30

Abstract: 29C948 ITR24
Contextual Info: Tem ic 29C948 MATRA MHS 8 Channel HDLC/V. 120 Protocol Controller Introduction The 29C948 is an 8 channel data link protocol controller circuit. It multiplexes/demultiplexes up to 8 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or clear

AD10

Abstract: AD11 AD12 AD14 AD17
Contextual Info: 29C948 MATRA MHS 8 Channel HDLC/V.120 Protocol Controller Introduction The 29C948 is an 8 channel data link protocol controller circuit. It multiplexes/demultiplexes up to 8 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or clear

ir transmitter receiver

Abstract: IRDA module UART Si9961CY transceiver rs232 driver receiver
Contextual Info: Tem ic S e m i c o n d u c t o r s SO 16 ^ S024 Mass Storage ICs : PärtNüBiber Function Key Features Package Source Disk-Drive/ Optical Drive ICs SÌ9961CY VCM driver • Cost-effective solution • No dead band • Zero cross over distortion S024 SC Interface ICs

One-chip telephone IC

Abstract: telephone line voice amplifier Voice to e1 converter circuit U 4076 One-chip telephone cordless IC VN2410* mosfet BFP67 slc96 remote terminal E1 PCM encoder V30 CPU
Contextual Info: TEMIC Semiconductors Communication Segment Digital Networks Wireless Communication Wired Communication Communication We’ve been supporting advances in communications industry for decades. Today, we continue to offer the best combination of applications knowledge and leading-edge solutions required by the

EIT30

Abstract: 29C93
Contextual Info: T e m ic 29C98 MATRA MHS B-Channel Resynchronizer Description ISDN public networks CENTRAL OFFICES usually implement channel switching except on leased lines. When higher data rates than 64 kbps are required between two terminals or between a terminal and a

tsr1-24

Abstract: mxt 211 RSR1-24 B18 IC marking code EL B17
Contextual Info: Tem ic 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formater Description T he 29C96 is a program m able CM OS device interfacing with T1 DS1 or E l (CEPT) transceivers. T he 29C96 supports following fram e form ats : • DS1 : 4 fram es (D M I), D4 (G704), ESF (G704),

29C841

Abstract: 29C841/
Contextual Info: AMD i l REVISIONS LTR D E SC RI PTI ON PATE YR-MO-PA Add PRESET and CLEAR propagation delays to table I for device types 02 and 04. Change figure 4. Editorial changes throughout. APPROVEO 88/07/22 Added devices 05 and 06. Changes to table I. Editorial changes throughout.

mxt 211

Contextual Info: Tem ic 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formatter Description The 29C96 is a programmable CMOS device interfacing with T1-DS1 or El-CEPT transceivers. The 29C96 supports following frame formats : • DS1 : 4 frames DMI , D4 (G704), ESF (G704), SLC-96 (DMI), DDS (DMI)

MQFPF256

Abstract: LCC68
Contextual Info: Tem ic S e m i c o n d u c t o r s PLCC28 S 028 On-Board Computers Part Number Function Key Features Package Source TSC691E 32-bit SPARC computer: integer unit Radiant tolerant, 10 Mips @ 14 MHz, JTAG interface MQFPF256 NT TSC692E 32-bit SPARC computer: floating-point unit

Contextual Info: Tem ic 29C95 MATRA MHS Multi-Channel ECMA 102/VI 10 Protocol Controller Description T he M HS 29C95 is a m ulti-channel data link protocol controlller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support im plem entation of data links based on either the

mxt 211

Abstract: signalling and frame alignment in E1 G704 SLC96 alarm frame format b30 c300 - 1 tsr1-24
Contextual Info: 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formatter Description The 29C96 is a programmable CMOS device interfacing with T1-DS1 or E1-CEPT transceivers. The 29C96 supports following frame formats : D DS1 : 4 frames DMI , D4 (G704), ESF (G704), SLC-96 (DMI), DDS (DMI)

BCR131

Abstract: 448H IT28 PCM255
Contextual Info: 29C98 MATRA MHS B-Channel Resynchronizer Description ISDN public networks CENTRAL OFFICES usually implement channel switching except on leased lines. When higher data rates than 64 kbps are required between two terminals or between a terminal and a server or host machine, and normal ISDN connection

29C843A

Abstract: 29c843
Contextual Info: REVISIONS DATE YR-MO-DA DESCRIPTION LTR Add PRESET and CLEAR propagation delays to table I for device types 02 and 04. Change figure 4. Editorial changes throughout. 88/07/22 Added devices 05 and 06. Changes to table I, Editorial changes throughout. 92/11/02

JFET TRANSISTOR REPLACEMENT GUIDE j201

Abstract: UA6538 DC motor speed control using 555 and ir sensor U2740B-FP UAA145 CQY80 U2840B tcrt9050 TCDF1910 sod80 smd zener diode color band
Contextual Info: Semiconductors Technical Library March 1996 Back Products Overview Communications Automotive Computer Industrial Broadcast Media Aerospace & Defense Communications Applications Telephone ICs Type U3750BM–CP Package 44–pin PLCC Function One chip telephone

5962L0053605VYC

Abstract: 5962-9069204QXA ATMEL 302 24C16 UT9Q512E-20YCC MOH0268D UT54ACS164245SEIUCCR Z085810 5962-9762101Q2A UT28F256QLET-45UCC 5962R0250401KXA
Contextual Info: NOT MEASUREMENT SENSITIVE MIL-HDBK-103AJ 19 SEPTEMBER 2011 SUPERSEDING MIL-HDBK-103AH 28 MARCH 2011 DEPARTMENT OF DEFENSE HANDBOOK LIST OF STANDARD MICROCIRCUIT DRAWINGS This handbook is for guidance only. Do not cite this document as a requirement. AMSC N/A