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    ITR17 Search Results

    ITR17 Datasheets (6)

    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    ITR17052
    		Unknown Cross Reference Datasheet Scan PDF 33.33KB 1
    ITR17052
    		Unknown Shortform Data and Cross References (Misc Datasheets) Short Form PDF 36.79KB 1
    ITR17052
    		Unknown Shortform IC and Component Datasheets (Plus Cross Reference Data) Short Form PDF 103.09KB 1
    ITR17053
    		Unknown Cross Reference Datasheet Scan PDF 33.33KB 1
    ITR17053
    		Unknown Shortform Data and Cross References (Misc Datasheets) Short Form PDF 36.79KB 1
    ITR17053
    		Unknown Shortform IC and Component Datasheets (Plus Cross Reference Data) Short Form PDF 103.09KB 1

    ITR17 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    DM 311 BG 40

    Abstract: DM 311 BG 42 K/DM 311 BG 29 DM 311 BG 30
    Contextual Info: Tem ic 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description T he MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support im plem entation of high speed data links based on


    OCR Scan     		29C94 29C94 29C3XX 29C96, DM 311 BG 40 DM 311 BG 42 K/DM 311 BG 29 DM 311 BG 30 PDF

    ITR17

    Abstract: ITR24 80X86 AD10 AD11 AD12 AD14 ITR28
    Contextual Info: 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description The MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or


    Original     		29C94 29C94 ITR17 ITR24 80X86 AD10 AD11 AD12 AD14 ITR28 PDF

    ITR30

    Abstract: 29C948 ITR24
    Contextual Info: Tem ic 29C948 MATRA MHS 8 Channel HDLC/V. 120 Protocol Controller Introduction The 29C948 is an 8 channel data link protocol controller circuit. It multiplexes/demultiplexes up to 8 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or clear


    OCR Scan     		29C948 29C948 ITR30 ITR24 PDF

    AD10

    Abstract: AD11 AD12 AD14 AD17
    Contextual Info: 29C948 MATRA MHS 8 Channel HDLC/V.120 Protocol Controller Introduction The 29C948 is an 8 channel data link protocol controller circuit. It multiplexes/demultiplexes up to 8 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or clear


    Original     		29C948 29C948 AD10 AD11 AD12 AD14 AD17 PDF