25FLTBB2 Search Results

1221H

Abstract: 32kx8 sram 32KX8 A12C CYM1420PD-20C cs 2502
Contextual Info: CYPRESS SEMICONDUCTOR bSE ]> • 25flTbb2 D01DÖS2 1Ö7 B K Y P CYM1420 CYPRESS SEMICONDUCTOR 128K X 8 Static RAM Module Features Functional Description • H igh-density 1-m egabit SRAM m odule T h e CY M 1420 is a very high perform ance 1-m egabit static R A M m odule organized

CY7C263-35PC

Abstract: 7C261 CY7C263 CY7C26345DMB cerdip z PACKAGE 7C264 C261 CY7C261 CY7C264 f1b0
Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) — 770 m\V (military) • Super low standby power (7C261)

2561b

Abstract: CPU 314 IFM 8kx1 RAM cy17 ALI chipset fast page mode dram controller CY2254ASC-2 CY27C010 CY82C691 CY82C693
Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support for standard 72-bit-wide DRAM banks Supports non-symmetrical DRAM banks

27c256-200

Abstract: 27C256-70 eprom 27c256 27C256-3 cerdip z PACKAGE eprom 27c256 28 PIN DIP 150 NS 27C256 27C256-2 27C256-45 CY27C256
Contextual Info: V CY27C256 CYPRESS Features • W ide speed range — 45 ns to 200 ns com m ercial and m ilitary • Low power — 248 raW (commercial) — 303 mW (m ilitary) • Low standby power — Less th a n 83 raW when deselected • ± 10% Power supply tolerance

CY7C3381A

Abstract: CY7C3381A-0JC CY7C3381A-0JI CY7C3381A-XJC CY7C3382A CY7C3384A CY7C3385A 00252-B
Contextual Info: CY7C3381A CY7C3382A CYPRESS Features • Very high speed — Loadable counter frequencies greater than SO MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithmetic, and random logic

w12 diode

Abstract: 7C243 cerdip z PACKAGE CY7C243 CY7C244
Contextual Info: CY7C243 CY7C244 W j? c y p r e s s • F e a tu re s • C M O S for optim um speed/pow er 4K X 8 Reprogrammable PROM C apable o f w ith stan d in g greater th an 2001V sta tic discharge • T T L -com patible I/O • D irect replacem ent for bipolar PR O M s

c225a

Contextual Info: y7CYPRESS= ^ = = = = 1^ = CY7C225A 512 x 8 Registered PROM • Slim 300-m il, 24-pin p la stic or her­ m etic DIP, 28-pin LC C, o r 28-p in PLCC T h e m e m o ry cells u tiliz e p ro v e n E P R O M flo a tin g g a te tech n o lo g y a n d by te-w id e in ­

Contextual Info: CY7C106A PRELIMINARY y CYPRESS 256K x 4 Static RAM Features Functional D escription • High speed T he CY7C106A is a high-perform ance CM O S static R A M organized as 262,144 words by 4 bits. Easy m em ory expansion is provided by an active LO W chip enable

Contextual Info: CY74FCT16823T CY74FCT162823T '0 C Y P R E S S 18-Bit Registers Features CY74FCT16823T Features: • Low power, pin compatible replacement for ABT functions • 64 mA sink current Com’l , 32 mA source current (Com’l) • FCT-C speed at 6.0 ns • TVpical V o l p (ground bounce)

TL 1838

Contextual Info: 128K x 32 Static RAM Module Features Functional Description • High-density 4-megabit SRAM module The CYM1838 is a very high perform ance 4-megabit static R A M m odule organized as 128K words by 32 bits. T he m odule is constructed using four 128K x 8 static

core i5 MOTHERBOARD block diagram

Contextual Info: I C d e s ig n s Motherboard Frequency Synthesizers ICD2093 “Super-Buffer” Clock Generator Single-Chip Oscillator for Use with Pentium Processor Based & Other High-Performance Systems Selectable CPU Clock Pro­ vides 8 2X or 1X outputs which Handle all Pentium™ Proces­

Contextual Info: W ? CYPRESS 64K x 24 Static RAM Module Features Functional D escription • High-density 1.5M SRAM module T h e CYM1730 is a high-perform ance 1.5M static RA M m odule organized as 64K words by 24 bits. This m odule is con­ structed using six 32K x 8 static R A M s in

Contextual Info: fax id: 5004 CY7B923 CY7B933 H O TLink T ra n sm itte r/R e ce ive d Features • • • • • • • • • • • • • • • • • twisted pair at data rates from 160 to 330 Mbits/second 400 Mbits/second for -400 devices). Figure 1 illustrates typical

CY7C429-25PC

Abstract: CY7C420 CY7C421 CY7C425 CY7C429 IDT7201 IDT7202 IDT7203 CY7C429-30DC vcy7
Contextual Info: bSE D • S S ö ^ b b E O O l O bB l bTD I CYPRESS SEMICONDUCTOR CYPRESS SEMICONDUCTOR ICYP CY7C420, CY7C421 CY7C424, CY7C425 CY7C428, CY7C429 Cascadable 512 x 9 FIFO Cascadable lK x 9 FIFO Cascadable 2K x 9 FIFO • TTL compatible • Three-state outputs

12L10

Abstract: 16L6 18L4 20L10 20L8
Contextual Info: PLD20G10C i f CYPR ESS Features • 10 user-programmable output macrocells — Output polarity control — Registered or combinatorial operation — Pin or product term output enable control • Ultra high speed supports today’s and tomorrow’s fastest microprocessors

STATIC RAM 6264

Abstract: 6264 static RAM 6264 RAM ram 6264 6264 CY6264 OC821 62645
Contextual Info: PRELIMINARY CYPRESS CY6264 8K x 8 Static RAM active HIGH chip enable CE2 , and active LOW output enable (OE) and three-state drivers. Both devices have an automatic power-down feature (CEi), reducing the power consumption by over 70% when de­ selected. The CY6264 is packaged in a

mt3351

Abstract: Cyrix 486 dx2 MT332 cyrix 486 Port70H 18L15 intel 486 dx4 386 MOTHERBOARD 82c597 cx486
Contextual Info: PRELIMINARY CYPRESS Features • 160-Pin single chip PQFP • Supports PC/AT compatible systems at 25/33/40/50 MHz • Supports AMD, Cyrix level 1 write­ back CPU • Write-Back/Write-Through cache with 32KB/64KB/128KB/256KB/512KB/ 1MB cache size • Non-cachable memory range support

led clock circuit diagram

Abstract: CY2252PVC-1 MF423
Contextual Info: fax id: 3522 CY2252 CYPR Mobile Pentium Processor Compatible Clock Synthesizer/Driver Features Multiple clock outputs to meet requirements of mobile systems using Pentium™ processors — Five CPU clocks @ 66.66 MHz, 60.0 MHz, 50.0 MHz or 33.33 MHz pin selectable

3 DG 1008

Abstract: MRF 530 PEWI CY7C451 CY7C453
Contextual Info: n r CYPRESS • • • • • • • • • • • • • 512 x 9 Cascadable Clocked and 2K x 9 Cascadable Clocked FIFOs with Programmable Flags Functional D escription Features • CY7C451 CY7C453 512 x 9 CY7C4S1 an d 2,048 x 9 (CY7C453) FIFO buffer m em ory

logic block diagram of cypress flash 370 device

Abstract: cypress flash 370 device SEM03 features cypress flash 370 7C371-2
Contextual Info: 7C373: Thursday, September 24,1992 .Revision: Monday,January4,1993 S7E D • 2 5 f l T L > t iE 00CH031 41E CYPRESS SEMICONDUCTOR ^ ^ s ts s s s 'Z ^ ^ i is m = ^ 'T'^' ci- PRELIMINARY Q Y PR ESS . • 128 macrocells in eight logic blocks

Contextual Info: CY7C344 CY7C344B y CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

Contextual Info: fax id: 3026 CY27C256A w CYPRESS 32K x 8 CMOS EPROM Features 28-pin, 600-mil DIP, 32-pin LCC and PLCC, and 28-pin TSOP-I packages. The CY27C256A is available in windowed and opaque packages. Windowed packages allow the device to be erased with UV light for 100% reprogrammability.

Contextual Info: fax id: 3501 IC D 2 0 6 1 A Dual Programmable Graphics Clock Generator Features • Second generation dual oscillator graphics clock gen­ erator • 2 independent clock outputs from 390 KHz to 100 MHz • Individually programmable oscillators using a highly

Contextual Info: CY54/74FCT373T CY54/74FCT573T Wfp CYPRESS 8-Bit Latches Features • E S D > 2000V • Function, pinout and drive compatible with the fastest bipolar logic • Fully compatible with T T L input and output logic levels • FCT-C speed at 4.2 ns max. Com’l