256PBGA Search Results

QL3004

Abstract: PLCC-84 QL3060 QL2003 QL2005 QL2007 QL2009 QL3012 QL3025 QL3040
Contextual Info: QuickSheet#4 pASIC FPGA Families High-Speed, Low Power, Instant-On, High Security FPGAs pASIC Family Highlights • High performance over 400 MHz • 100% routability and pin stability • Instant-On capability • High security and reliability • Low power

ad 161

Abstract: vhdl code PN code generator ad 152 transistor ad 153 transistor S-108 PF144 PQ208 QL5130 QL5130-33APF144C QL5130-33APQ208C
Contextual Info: QL5130 - QuickPCITM 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM last updated 12/1099 Device Highlights DEVICE HIGHLIGHTS Q8DÃ7ˆ†Ã±Ã""ÃHC“Ã"!Ãiv‡†Ãqh‡hÃhqÃhqq…r†† High Performance PCI Controller • 32-bit / 33 MHz PCI Target

GC1115

Contextual Info: GC1115 www.ti.com SLWS144 – FEBRUARY 2005 Crest Factor Reduction Processor FEATURES APPLICATIONS • • • • • • • • • • • • • • Significantly Reduces Signal Peaks to ≥ 6 dB PAR One 20-MHz or 2 Independent 10-MHz Channels Programmable Output PAR Down to 6 dB

GC1115

Contextual Info: GC1115 www.ti.com SLWS144 – FEBRUARY 2005 Crest Factor Reduction Processor FEATURES APPLICATIONS • • • • • • • • • • • • • • Significantly Reduces Signal Peaks to ≥ 6 dB PAR One 20-MHz or 2 Independent 10-MHz Channels Programmable Output PAR Down to 6 dB

QL4090

Abstract: pASIC 1 Family 160CQFP 208-CQFP
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

208CQFP

Contextual Info: QL2007  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

A42 B331

Abstract: CA91C860B-40IQ CA91C860B-40CQ CA91C860B-50CQ tea 1601 t CA91C860B a44 b331 CA91C860 T337A CA91L860B-50CE
Contextual Info: QSpan CA91C860B, CA91L860B PCI to Motorola Processor Bridge Manual http://www.tundra.com The information in this document is subject to change without notice and should not be construed as a commitment by Tundra Semiconductor Corporation. While reasonable precautions have been taken, Tundra

ejtag

Abstract: 79RC32334 FCT245 MIPS32 RC32300 RC32364 RC5000 IDT79RC32V334
Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

SB21150BC

Abstract: SB21150AC GD21150BC dc1111d SB21150 DC1030G 74ls166 21150-AC SB21150-AC GD21150AC
Contextual Info: 21150 PCI-to-PCI Bridge Specification Update October 2001 Notice: The 21150 may contain design defects or errors known as errata. Characterized errata that may cause the 21150’s behavior to deviate from published specifications are documented in this specification update.

voip

Abstract: BCM1112 cable gateway reference design MIPS32 application BCM1101 MIPS32 VOCODERS voip "Power over Ethernet"
Contextual Info: BCM1112 VOICE OVER IP CPE ENGINE FEATURES • The BCM1112 is the most highly integrated silicon solution for Ethernet Residential Gateway and Stand-Alone Media Terminal Adapter applications. • The BCM1112 Integrates: • 150-MHz MIPS32 CPU 165 DMIPS with 8K I-cache and 4K

Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334—Rev. Y Preliminary Information* Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

QL5130-33APF144C

Abstract: QL5130 QL5130-33APQ208C QL5130-33APQ
Contextual Info: QL5130 QuickPCI Data Sheet • • • • • • 33 MHz/32-Bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller Programmable Logic • 57 K system gates/619 logic cells • 13,824 RAM bits, up to 157 I/O pins

Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334—Rev. Y Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

GDS1110BD

Abstract: GDS1110BC GDS1110AD GDS1110 GDS1110BB bau 95 SA-1110 B010 FP3031 GDS1110AC
Contextual Info: Intel StrongARM* SA-1110 Microprocessor Specification Update April 2001 Notice: The SA-1110 may contain design defects or errors known as errata. Characterized errata that may cause the SA-1110’s behavior to deviate from published specifications are documented in this

tms 1951 nl

Abstract: alcatel 1511 max sf12 "pin compatible"
Contextual Info: Intel IXF3208 Octal T1/E1/J1 Framer with Intel® On-Chip PRM Datasheet Product Features • ■ ■ ■ ■ ■ ■ ■ ■ Octal T1/E1/J1 Framer Software selectable and fully independent T1/E1/J1 operation Support for T1/E1/J1 standards: — T1: T1-SF, T1-ESF, Lucent* SLC®96

pasic 3

Abstract: QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060
Contextual Info: pASIC 3 FPGA Family Data Sheet •••••• Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • Up to 60,000 usable PLD gates with up to 316 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths

79RC32334

Abstract: FCT245 MIPS32 RC32300 RC32364 RC5000
Contextual Info: 79RC32334—Rev. Y IDTTM InterpriseTM Integrated Communications Processor Features Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

GDS1110BD

Abstract: GDS1110BC GDS1110 ICL7071 GDS1110BB PL-2305 GDS1110AD spi flash mpc programmer SA-1110 UCB1300
Contextual Info: Intel StrongARM* SA-1110 Microprocessor Developer’s Manual October 2001 Notice: Verify with your local Intel sales office that you have the latest technical information before finalizing a design. Order Number: 278240-004 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

FPGA 144 CPGA ASIC

Abstract: QL5032 144TQFP PACKAGE 160-CQFP PLCC 144
Contextual Info: p ASIC QUICKLOGIC DEVELOPMENT TOOLS Part Number Product Name QS-QWK-PC QuickWorks QS-QTL-WS QuickTools for Workstations N/A QuickWorks - Lite N/A QuickMap QT-DFP-PC-A 1 DeskFab Programmer Kit N/A Synosys Interface Kit N/A Viewlogic Interface Kit N/A Mentor Interface Kit

laf 0001 for power supply of LCD monitor diagram

Abstract: laf 0001 LCD monitor diagram laf 0001 power ic laf 0001 PWM Control laf 0001 ic Substitution str g 8656 str 8656 DISPLAY VGA 6448 10.4 EP89712 STR G 8654
Contextual Info: CS89712 High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller Features – Automatic Padding and CRC Generation l Programmable Receive Features: l ARM720T processor – Early Interrupts for Frame Pre-Processing – Automatic Rejection of Erroneous Packets

IXF3208

Contextual Info: Cortina Systems IXF3208 Octal T1/E1/ J1 Framer Datasheet Product Features „ „ „ Octal T1/E1/J1 Framer Software selectable and fully independent T1/E1/J1 operation Support for T1/E1/J1 standards: „ — BERT generators and analyzers for extensive on-chip error testing

ph08

Contextual Info: LH7A400 32-Bit System-on-Chip Data Sheet FEATURES • Smart Card Interface ISO7816 • 32-bit ARM9TDMI RISC Core – 16KB Cache: 8KB Instruction and 8KB Data – MMU (Windows CE™ Enabled) – Up to o 250 MHz; see Table 1 for options • Two DC-to-DC Converters

AMBA AHB bus protocol

Abstract: M316 arm microprocessor data sheet lcd N7 SA2 Schottky schematic diagram sharp lcd 5819 TIME CLOCK CMOS RAM CONVERTER AMBA APB bus protocol express card T0 USB mmc-1
Contextual Info: LH7A400 32-Bit System-on-Chip Preliminary Data Sheet FEATURES • Three Programmable Timers • ARM922T Core: – 32-bit ARM9TDMI™ RISC Core – 16KB Cache: 8KB Instruction Cache and 8KB Data Cache – MMU Windows CE Enabled • Three UARTs – Classic IrDA (115 kbit/s)