QL3006 Search Results

Contextual Info: QL3006 pASIC 3 FPGA Data Sheet •••••• 6,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance and High Density • 6,000 usable PLD gates with 82 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths

asynchronous fifo vhdl

Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024
Contextual Info: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com

pasic 3

Abstract: QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060
Contextual Info: pASIC 3 FPGA Family Data Sheet •••••• Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • Up to 60,000 usable PLD gates with up to 316 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths

QL3004

Abstract: QL3004-1PL68C QL3004E QL3012 QL3004-1PL84C QL3006 QL3025 QL3040 QL3060
Contextual Info: pASIC 3 FPGA Family Data Sheet •••••• Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • Up to 60,000 usable PLD gates with up to 316 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths

QL3006

Contextual Info: 4/ S$6,&  3*$ 'DWD 6KHHW ‡‡‡‡‡‡  8VDEOH 3/' *DWH S$6,&  )3*$ &RPELQLQJ +LJK 3HUIRUPDQFH DQG +LJK 'HQVLW\ 'HYLFH +LJKOLJKWV +LJK 3HUIRUPDQFH +LJK 'HQVLW\ ‡ 6,000 Usable PLD Gates with 82 I/Os ‡ 300 MHz 16-bit Counters, 400 MHz Datapaths