245IS Search Results

Contextual Info: Â B V I î » A e ro s p a c e /R u g g e d :zöd Printed Circuit Board C o nnectors Catalog 296 350 Issued 9 -9 7 4-Row Receptacle A s s e m b l ie s .060 T I H o u s in g M a t e r ia l f^ciyp t'eilylen:.-: .is o [3.31 s.illirlf; pet MIL M 245IS nr type

Contextual Info: IS93C46 '. d ISSI i 1024-BIT SERIAL ELECTRICALLY ERASABLE PROM WITH 2V READ CAPABILITY FEATURES PRELIMINARY August 1990 PIN CONFIGURATIONS • State-of-the-Art Architecture — Non-volatile data storage — Single supply - 5V operation — Full TTL compatible inputs and outputs

Contextual Info: ISSI PRELIMINARY 2048-BIT SERIAL ELECTRICALLY ERASABLE PROM WITH 2V READ CAPABILITY FEATURES August 1990 PIN CONFIGURATIONS • State-of-the-Art Architecture — Non-volatile data storage — Single supply - 5V operation — Full TTL compatible inputs and outputs

61C416

Abstract: IS61C416
Contextual Info: IS 61C416 ISSI v ili 4K X 16 HIGH SPEED CMOS CACHE RAM PRELIMINARY OCTOBER 1990 FEATURES DESCRIPTION • High speed access time - 2 5 ,3 5 ,45ns Max. • Designed for 80386 Cache system: 25ns - 33MHz 35ns - 25MHz 45ns - 20MHz The ISSI IS61C416 is a very high speed, low power, 4096

733-ISSI

Contextual Info: 16KX1 HIGH SPEED CMOS STATIC RAM PRELIMINARY OCTOBER 1990 FEATURES DESCRIPTION • High speed access time 15,20,25ns Max. • Low active power- 200mW (Typical) • Low standby power-55mW (Typical) TTL standby -10(iW (Typical) CMOS standby (L-version) • Fully static operation-no clock or refresh required

61C30

Abstract: 82385
Contextual Info: IS 61C308 2 X 2K X 16 HIGH SPEED CMOS CACHE RAM PRELIMINARY OCTOBER 1990 FEATURES DESCRIPTION • High speed acces time - 2 5 ,3 5 ,45ns Max. • Designed for 80386 Cache system: 25ns - 33MHz 35ns - 25MHz 45ns - 20MHz The ISSI IS61C308 is a high speed, low power, two banks of

Contextual Info: ISSI IS 61C68 4K X 4 HIGH SPEED CMOS STATIC RAM AUGUST 1990 FEATURES DESCRIPTION • • • The ISSI IS61C68 is a high speed, low power, 4096- word by 4- bit CMOS static RAM. It is fabricated using ISSI's high performance CMOS double metal technology. This highly

IS61C67-15N

Abstract: 733-ISSI
Contextual Info: HH -gli IS 61C67 ISSI 1 6 KX1 HIGH SPEED CMOS STATIC RAM PRELIMINARY OCTOBER 1990 FEATURES DESCRIPTION • High speed access time 15,20,25ns Max. • Low active power- 200mW (Typical) • Low standby power-55mW (Typical) TTL standby -10|iW (Typical) CMOS standby (L-version)

62c1024

Abstract: IS62C1024 CE121
Contextual Info: IS 62C1024 ISSI 'm s*' ? 128K X 8 LOW POWER CMOS STATIC RAM PRELIMINARY OCTOBER 1990 FEATURES DESCRIPTION • The ISSI IS62C1024 is a high speed, low power, 131,072- word by 8- bit CMOS static RAM. It is fabricated using ISSI's high performance CMOS double metal technol­

OF sk 733

Abstract: 93C66 93c66 issi f 93c66 txal IS61C416 chip 8-pin 93C66 IS93C66
Contextual Info: ISSI IS93C66 4096-BIT SERIAL ELECTRICALLY ERASABLE PROM WITH 2V READ CAPABILITY FEATURES PRELIMINARY August 1990 PIN CONFIGURATIONS • State-of-the-Art Architecture — Non-volatile data storage — Single supply - 5V operation — Full TTL compatible inputs and outputs

61c1024

Abstract: IS61C1024
Contextual Info: IS 61C1024 128K X 8 HIGH SPEED CMOS STATIC RAM PRELIMINARY SEPTEMBER 1990 DESCRIPTION FEATURES The ISSI IS 6 lC l0 2 4 is a high speed, low power, 131,072- word by 8- bit CMOS static RAM. It is fabricated using ISSI's high performance CMOS double metal technol­

82C481

Abstract: 82C381 opti 82C481 OPTI 82C281 FACT521A opti 82c381
Contextual Info: IS 61C81 j ISSI •v!! ■ :/iÀ 8K X 8 - BIT CACHE TAG CMOS STATIC RAM PRELIMINARY OCTOBER 1990 FEATURES DESCRIPTION • • • • The ISSI IS61C81 is a very high speed cache address comparator sub-system consisting of a 65,536-bit static RAM organized as 8K x 8. Cycle Time and Compare Access Time

Contextual Info: ISSI •T 3T 51 *• > 1 IS 61C816 2 x 4K x 16, 8K X 16 HIGH SPEED CMOS CACHE RAM OCTOBER1990 DESCRIPTION FEATURES • PRELIMINARY The ISSI IS61C816 is fabricated by the double layer polysili­ con, double layer metal CMOS technolgy. It is specifically designed to provide direct interface to the 80386 32-bit CPU

93C46 CMOS Serial Electrically Erasable PROM

Abstract: 93c46 LN 93c46 st IS93C46 chip 8-pin 93C46 ISSI 93C46
Contextual Info: IS93C46 ISSI * 1024-BIT SERIAL ELECTRICALLY ERASABLE PROM WITH 2V READ CAPABILITY PRELIMINARY August 1990 PIN CONFIGURATIONS FEATURES • State-of-the-Art Architecture — Non-volatile data storage — Single supply - 5V operation — Full TTL compatible inputs and outputs

Contextual Info: ISS 3 4K X 4-BIT CACHE-TAG CMOS STATIC RAM OCTOBER 1990 FEATURES DESCRIPTION • Very High Speed -1 2 ,1 5 , 20ns Max. • Fast output enable (tOE) for cache applications • CMOS Low Power Operation The ISSI IS61C180 is a high-speed, low power 4096 words by 4 bit static RAM. It is fabricated using ISSI's high

IS61C66-20N

Contextual Info: ISSI IS 61C66 16KX4 HIGH SPEED CMOS STATIC RAM AUGUST 1990 FEATURES DESCRIPTION • • • The ISSI IS61C66 is a very high speed, low power, 16384 words by 4 bit static RAM. The device is fabricated using ISSI's high performance CMOS double metal technology.

61c64

Abstract: IS61C64-S20W IS61C64-S20N IS61C64 IS61C64-S20P
Contextual Info: ISSI IS61C64_ U 8K X 8 HIGH SPEED CMOS STATIC RAM FEATURES • • • • • • • • • • Very High Speed - 20, 25, 30 ns Max. Fast output enable (tOE) for cache applications Automatic power-down when chip is deselected CMOS Low Power Operation

61c88

Contextual Info: ISSI IS 61C88 16K X 4 HIGH SPEED CMOS STATIC RAM AUGUST 1990 FEATURES DESCRIPTION • • • • The ISSI IS61C88 is a very high speed, low power, 16384 words by 4 bit static RAM. The device is fabricated using ISSI's high performance CMOS double metal technology.

62C256

Contextual Info: IS 62C256 ISSI - JïOv* 32K X 8 LOW POWER CMOS STATIC RAM PRELIMINARY OCTOBER 1990 FEATURES DESCRIPTION • Fast Access Time: 8 0 ,1 0 0 ,120ns max. • Low Power Dissipation Standby (CMOS): 10nW(typ.) Operating: 250mW (max.) The ISSI IS62C256 is a high speed, low power, 32,768-word

Contextual Info: IS 62C1024 128K X 8 LOW POWER CMOS STATIC RAM PRELIMINARY OCTOBER 1990 FEATURES DESCRIPTION Low active power- 75mW Typical High speed access tim e-70,8 5 ,100ns (Max.) Low standby power-1 O^iW (Typical) CMOS standby (L-version) Output enable and two chip enable inputs for ease

Contextual Info: ISSI IS93C66 4096-BIT SERIAL ELECTRICALLY ERASABLE PROM WITH 2V READ CAPABILITY FEATURES PRELIMINARY August 1990 PIN CONFIGURATIONS • State-of-the-Art Architecture — Non-volatile data storage — Single supply - 5V operation — Full TTL compatible inputs and outputs

Contextual Info: ISSI IS93C46-3 1024-BIT SERIAL 3V TO 5V ELECTRICALLY ERASABLE PROM WITH 2V READ CAPABILITY FEATURES PRELIMINARY August 1990 PIN CONFIGURATIONS • State-of-the-Art Architecture — Non-volatile data storage — 3V to 5V operation — Full TTL compatible inputs and outputs

Contextual Info: ISSI IS 61C88 16K X 4 HIGH SPEED CMOS STATIC RAM AUGUST 1990 FEATURES DESCRIPTION • Very High Speed - 15, 20, 25, 30 ns Max. • Fast output enable (tDOE) for cache applications • • Automatic power-down when chip is deselected CMOS Low Power Operation

IS61C64-25N

Abstract: IS61C64-20N 61c16 IS61C64-25J IS61C64-20 IS61C64
Contextual Info: ISST 2K X 8 HIGH SPEED CMOS STATIC RAM PRELIMINARY OCTOBER 1990 FEATURES DESCRIPTION • The ISSI IS61C16 is a very high speed, low power, 2048 words by 8 bit static RAM. It is fabricated using ISSI's high performance CMOS double metal technology. This highly