231369 Search Results

Intel 1702 eprom

Abstract: 231369 INTEL 24 PIN CERAMIC DUAL-IN-LINE PACKAGE Side Brazed Ceramic Dual-In-Line Packages PACKAGE/MODULE/PC CARD OUTLINES AND DIMENSIONS 64 CERAMIC LEADLESS CHIP CARRIER LCC CERAMIC PIN GRID ARRAY CPGA lead frame CERAMIC PIN GRID ARRAY CPGA lead frame 325 Intel 2164 Side Brazed Ceramic Dual-In-Line Packages 28
Contextual Info: 2 2 Package/Module/PC Card Outlines and Dimensions 1/20/97 6:33 PM CH02LINK.DOC INTEL CONFIDENTIAL until publication date 2 CHAPTER 2 PACKAGE/MODULE/PC CARD OUTLINES AND DIMENSIONS Intel Product Identification Codes 231369-1 2-1 1/20/97 6:33 PM CH02LINK.DOC

ocs4

Contextual Info: M80C186EB PACKAGE INFORMATION This section describes the pins, pinouts, and thermal characteristics for the M80C186EB PGA package. For complete package specifications and informa­ tion, see the Intel Packaging Outlines and Dimen­ sions Guide Order Number: 231369 .

D2764

Abstract: 2764A eprom
Contextual Info: intei 2764A 64K 8K x 8 UV ERASABLE PROMs inteligent Fast Access Time—HMOS* II E — 180 ns Cerdip D2764A-1 Id e n tif ie r Mode Industry Standard Pinout. . . JEDEC Approved . . . 28 Lead Package Moisture Resistant (See Packaging Spec, Order #231369)

PQFP 132 PACKAGE DIMENSION intel

Abstract: 82358 EISA chip set intel 82350 PQFP dimension intel DIMENSIONS PQFP 132 DIMENSIONS pqfp 100 82350 Intel PQFP 231369
Contextual Info: ¡ntéT M y M O N IM V 82350 MECHANICAL DATA Introduction PACKAGING INFORMATION See Packaging Spec. Order # 231369 The individual components of Intel’s EISA Chip Set come in JEDEC standard Gull Wing packages (25 MIL pitch), with "bumpers” on the corners for ease

block diagram 8259A

Abstract: 8259 intel 8259 8259 INTEL pin diagram 8259 8259 Programmable Interrupt Controller file intel 8259 programmable interrupt controller intel 8259a I8259A programmable interrupt controller 8259A
Contextual Info: in te i 8259A PROGRAMMABLE INTERRUPT CONTROLLER 8259A/8259A-2 • 8086, 8088 Compatible Single + 5V Supply (No Clocks) ■ MCS-80, MCS-85 Compatible Available in 28-Pin DIP and 28-Lead PLCC Package ■ Eight-Level Priority Controller (See Packaging Spec., Order #231369)

8086 interrupt vector table

Abstract: intel 8259A 8086 8259 interrupt controller opcode sheet for 8086 microprocessor 8086 logic diagram 76S43210 8259 PIC cmc03 interfacing 8259A to the 8086 8085A-2
Contextual Info: in te i 8259A PROGRAMMABLE INTERRUPT CONTROLLER 8259A/8259A-2 8086, 8088 Compatible Single + 5V Supply (No Clocks) MCS-80 , MCS-85" Compatible Available in 28-Pln DIP and 28-Lead PLCC Package Eight-Level Priority Controller (See Packaging Spec., O rder #231369)

interfacing 8259A to the 8086

Abstract: 8086 interrupt vector table block diagram 8259A intel 8259A ir417 8259A MCS-851 programmable interrupt controller 8259A MCS-80 MCS-85
Contextual Info: in te i 8259A PROGRAMMABLE INTERRUPT CONTROLLER 8259A/8259A-2 • 8086, 8088 Compatible Single + 5V Supply (No Clocks) ■ MCS-80 , MCS-85® Compatible Available in 28-Pin DIP and 28-Lead PLCC Package ■ Eight-Level Priority Controller (See Packaging Spec., Order #231369)

Contextual Info: Extract from the online catalog SUBCON-PLUS-PROFIB/90/SC Order No.: 2313698 D-SUB connector, 9-pos., male connector, cable entry < 90°, bus system: PROFIBUS DP up to 12 Mbps, termination resistor can

Contextual Info: intei 82284 CLOCK GENERATOR AND READY INTERFACE FOR iAPX 286 PROCESSORS 82284- 10, 82284- 8 , 82284- 6 • Generates System Clock for iAPX 286 Processors Available in 18-Lead Cerdip Package (See Packaging Spec, Order #231369) ■ Uses Crystal or TTL Signal for Frequency

231369

Abstract: TQFP 44 PACKAGE footprint NG80386SX16 Side Brazed Ceramic Dual-In-Line Packages CERAMIC PIN GRID ARRAY CPGA lead frame 325 A80486DX-25 TQFP 144 PACKAGE DIMENSION intel order 231369 600E12 BGA and QFP Package
Contextual Info: Package Module PC Card Outlines and Dimensions February 1996 Order Number 231369-012 PACKAGE MODULE PC CARD OUTLINES AND DIMENSIONS Intel Product Identification Codes 231369 – 1 EXAMPLES A80486DX25SX387 32-Bit Microprocessor 25 MHz 168-Lead Ceramic Pin Grid Array

EPROM 2764a

Abstract: 27C126 2764A1 2764A 2764A-1 eprom 2716 D2764A-1 2764A eprom 2764A-2 27C128 INTEL
Contextual Info: 2764A 64K 8K x 8 UV ERASABLE PROMs • Fast Access Time— HMOS* H E — 180 ns Cerdip D2764A-1 ■ Moisture Resistant ■ inteligent Identifier Mode a |ndustry standard Pinout. . . JEDEC Approved . . . 28 Lead Package ■ Two-line Control <See Packagin9 Spec' ° rder #231369)

EPROM 2764a

Abstract: 2764a eprom PINOUT eprom 2716 2764A1 2764A eprom 2764A-25 2764A 27C128 INTEL Eprom B 2716 D 2764A-1
Contextual Info: 2764A 64K 8K x 8 UV ERASABLE PROMs • Fast Access Tim e— HMOS* HE 180 ns Cerdip D2764A-1 ■ Moisture Resistant ■ inte ligent Id en tifier M ode a industry Standard Pinout. . . JEDEC Approved . . . 28 Lead Package ■ Two-line Control (SeePacka9ingSpec' ° rder #231369)

TE28F640J3C-120

Abstract: TE28F128J3C-120 INTEL 28F320J3 28F128J3 28F256K18 TE28F320J3C110 28F320J3 RC28F640J3C-120 28F640J3 28F640J3 reliability
Contextual Info: 3 Volt Intel StrataFlash Memory 28F128J3, 28F640J3, 28F320J3 x8/x16 Datasheet Product Features • ■ ■ Performance — 110/115/120/150 ns Initial Access Speed — 25 ns Asynchronous Page-Mode Reads — 32-Byte Write Buffer —6.8 µs per Byte Effective

IN6AG

Abstract: 28F020 intel 28F020
Contextual Info: 28F020 2048K 256K x 8 CMOS FLASH MEMORY • Flash Electrical Chip-Erase — 2 Second Typical Chip-Erase ■ Quick-Pulse Programming Algorithm — 10 ¡is Typical Byte-Program — 4 Second Chip-Program ■ 100,000 Erase/Program Cycles ■ 12.0V ± 5 % Vpp

Contextual Info: in te l 28F020 2048K 256K x 8 CMOS FLASH MEMORY Flash Electrical Chip-Erase — 2 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 jas Typical Byte-Program — 4 Second Chip-Program 100,000 Erase/Program Cycles 12.0V ± 5 % Vpp High-Performance Read

m8087 intel

Contextual Info: p R iy iM O B y w in te i M80C187 80-BIT NUMERIC PROCESSOR EXTENSION Military High Perform ance 80-Bit Internal Architecture Tw o to Three Tim es M8087 Perform ance at Equivalent Clock Speed Im plements A N S I/IE E E Standard 7541985 fo r Binary Floating-Point

intel 82310

Abstract: 82310 intel 80387sx intel 80386 motherboard,
Contextual Info: in te T 82310 Micro Channel COMPATIBLE PERIPHERAL CHIP SET • Highly Integrated VLSI Components to Implement Micro Channel Compatible Motherboard ■ Single Architectural Solution for 80386 16 MHz, 20 MHz and 25 MHz systems, and 80386SX 16 MHz Systems

AS085

Contextual Info: i r r t j , 8085AH/8085AH-2/8085AH-1 8-BIT HMOS MICROPROCESSORS • Single +SV Power Supply with 10% Voltage Margins ■ 3 MHz, 5 MHz and 6 MHz Selections Available ■ 20% Lower Power Consumption than 8085A for 3 MHz and 5 MHz ■ 1.3 ju.s Instruction Cycle 8085AH ; 0.8

Contextual Info: 28F256A 256K 32K x 8 CMOS FLASH MEMORY • Flash Electrical Chip-Erase — 1 Second Typical Chip-Erase ■ Quick-Pulse Programming Algorithm — 10 fis Typical Byte-Program — 0.5 Second Chip-Program ■ 100,000 Erase/Program Cycles ■ 12.0V ± 5 % Vpp

coprocessor

Contextual Info: in y Intel387 SX MATH COPROCESSOR N e w A u to m a tic P o w e r M a n a g e m e n t — L o w P o w e r C o n su m p tio n — T y p ic a lly 100 m A in D y n a m ic M o de, an d 4 m A in Id le M o d e S o c k e t C o m p a tib le w ith In te l3 8 7 Fam ily

Contextual Info: ir v tJ . 28F256A 256K 32K x 8 CMOS FLASH MEMORY • Flash Electrical Chlp-Erase — 1 Second Typical Chip-Erase ■ Command Register Architecture for Microprocessor/Microcontroller Compatible Write Interface ■ Quick-Pulse Programming Algorithm — 10 /j.8 Typical Byte-Program

intel 386 motherboard diagram

Abstract: 386SX chipset intel 82395sx 82395sx Intel 386 DX 82395dx Intel CPU 386
Contextual Info: SbE D in te ! • 4Ö2L17S DllS3b2 4T4 ■ I T L 1 INTEL CORP UP/PRPHLS 82311 ' •5 2 -3 > 3 -1 3 HIGH INTEGRATION Micro Channel COMPATIBLE PERIPHERAL CHIP SET Flexible Memory Architecture Support — Up to 4 Banks of Interleaved Page Memory — 256K, 1M, 4M DRAM Support

Contextual Info: ß lä § L 0M flß 9M f 87C75PF MICROCONTROLLER PERIPHERAL I/O PORT EXPANDER WITH 32Kx8 EPROM • 2 Configurable 8-bit I/O Ports — Open Drain — Quasi-bi-directional — CMOS ■ 32K x 8 EPROM — 200nS Access Time ■ Quick-Pulse Programming Algorithm

Contextual Info: in te i 1-MBIT 128K X 8 BOOT BLOCK FLASH MEMORY 2 8 F 0 0 1 B X -T /2 8 F 0 0 1 B X -B /2 8 F 0 0 1 B N -T /2 8 F 0 0 1 B N -B • High-Integration Blocked Architecture — One 8 KB Boot Block w/Lock Out — Two 4 KB Parameter Blocks — One 112 KB Main Block