225PS Search Results

K4161

Abstract: 89830U SY89830U SY89830UK4I SY89830UK4ITR 100KEP
Contextual Info: 2.5V/3.3/5V 2.5GHz 1:4 PECL/ECL CLOCK DRIVER WITH 2:1 DIFFERENTIAL INPUT MUX Micrel Precision Edge SY89830U Precision Edge™ SY89830U FEATURES • Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX • < 25ps within-device skew • < 225ps tr/tf time

MAX9325

Abstract: MAX9325EGI MAX9325EQI MC100LVE310
Contextual Info: 19-2511; Rev 2; 10/02 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver Features The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew 50ps max and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a

Contextual Info: 19-2511; Rev 3; 11/04 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver Features The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew 50ps max and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a

89830u

Abstract: SY89830U SY89830UK4G SY89830UK4GTR SY89830UK4I SY89830UK4ITR
Contextual Info: Micrel, Inc. 2.5V/3.3/5V 2.5GHz 1:4 PECL/ECL CLOCK DRIVER WITH 2:1 DIFFERENTIAL INPUT MUX Precision Edge SY89830U ® Precision Edge SY89830U FEATURES • Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX • < 25ps within-device skew • < 225ps tr/tf time

Contextual Info: 3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX ECL Pro SY100EP15V FINAL FEATURES • High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX toggle • < 225ps rise/fall times

Contextual Info: 3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX SY100EP15V FEATURES • High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX toggle • < 225ps rise/fall times • < 25ps within device skew

10n12

Contextual Info: 2.5V/3.3/5V 2.5GHz 1:4 PECL/ECL CLOCK DRIVER WITH 2:1 DIFFERENTIAL INPUT MUX FEATURES DESCRIPTION • Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX • < 25ps within-device skew • < 225ps tr/tf time • < 450ps prop delay ■ Low jitter design:

tip 1050

Abstract: SY89830U SY89831U SY89831UMI SY89831UMITR SY89832U SY89833U
Contextual Info: 2GHz ANY DIFF. IN-TO-LVPECL ULTRA LOWJITTER AND SKEW 1:4 FANOUT BUFFER/ TRANSLATOR W/ INTERNAL TERMINATION FEATURES SY89831U FINAL DESCRIPTION • Guaranteed AC performance over temperature and voltage • > 2.0GHz fMAX • < 20ps within-device skew • < 225ps rise/fall times

Contextual Info: 2.5V/3.3V TWO INPUT , 1GHz LVTTL/CMOS-TO-LVPECL 1:4 FANOUT BUFFER/TRANSLATOR FEATURES DESCRIPTION • Guaranteed AC performance over temperature and voltage: • > 1.0GHz fMAX • < 20ps within-device skew • < 225ps rise/fall times ■ Low jitter design:

3775 16 pin

Abstract: SY100EP15V SY100EP15VK4I SY100EP15VK4ITR
Contextual Info: 3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX FEATURES SY100EP15V Final DESCRIPTION • High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX toggle • < 225ps rise/fall times

SY89830U

Abstract: SY89831U SY89832U SY89834U SY89834UMI SY89834UMITR
Contextual Info: 2.5V/3.3V TWO INPUT , 1GHz Precision Edge LVTTL/CMOS-TO-LVPECL SY89834U 1:4 FANOUT BUFFER/TRANSLATOR FEATURES • Guaranteed AC performance over temperature and voltage: • > 1.0GHz fMAX • < 20ps within-device skew • < 225ps rise/fall times ■ Low jitter design:

Contextual Info: 2.5V/3.3V TWO INPUT , 1GHz PRELIMINARY Precision Edge LVTTL/CMOS-TO-LVPECL SY89834U 1:4 FANOUT BUFFER/TRANSLATOR FEATURES • Guaranteed AC performance over temperature and voltage: • > 1.0GHz fMAX • < 20ps within-device skew • < 225ps rise/fall times

MAX9325EGI

Abstract: MAX9325 MAX9325EQI MC100LVE310
Contextual Info: 19-2511; Rev 3; 11/04 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver Features The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew 50ps max and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a

AOI32

Contextual Info: SEEÚ TECHNOL OGY INC 11E I> • flina33 Q0027M4 0 E/M47F512 512K Bit CMOS FLASH EPROM October 1989 PRELIMINARY DATA SHEET Block Diagram Features ■ 64K Byte FLASH Erasable Non-Volatile Memory ■ Input Latches for Writing and Erasing ■ Fast Byte Write: 225ps max

sublvds to lvds

Abstract: sub-lvds sublvds TX B0177 link budget calculation 3 POSITION TOGGLE SWITCH 6 pin s0224 sublvds SLLS836 SN65LVDS305
Contextual Info: SN65LVDS310 www.ti.com SLLS836 – MAY 2007 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER FEATURES • • • • • • • • • • • Serial Interface Technology Compatible With FlatLink 3G Transmitters E.g., SN65LVDS305 or SN65LVDS307 Supports Video Interfaces up to 24-Bit RGB

SD-A29H0

Contextual Info: CRYSTAL CLOCK OSCILLATORS Data Sheet 0528A Rev. B Differential Positive ECL DPECL Fast Edge SD-A29H0 Series Description The SD-A29H0 Series of quartz crystal oscillators provide DPECL compatible signals. Systems designers may now specify space-saving, cost-effective packaged PECL oscillators to meet their timing requirements.

SN75LVDS81

Abstract: DS90C383A DS90C383AMTD DS90CF383A DS90CF383AMTD DS90CF384 SN75LVDS83
Contextual Info: General Description Features The DS90C383A/DS90CF383A transmitter converts 28 bits of CMOS/TTL data into four LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth

0528A

Abstract: SD-A29H0 tachyon dx4
Contextual Info: CRYSTAL CLOCK OSCILLATORS Data Sheet 0528A Rev. H Differential Positive ECL DPECL Fast Edge SD-A29H0 Series Description The SD-A29H0 Series of quartz crystal oscillators provide DPECL compatible signals. Systems designers may now specify space-saving, cost-effective packaged PECL oscillators to meet their timing requirements.

ecliptek emds12 series

Contextual Info: EMDS12 Series EMDS12 • MEMS Clock Oscillators • LVDS Output • +2.5V Supply Voltage • Complementary Output • Output Enable and Standby Options • 6 Pad Plastic SMD Package • 30,000 G Shock Resistance • RoHS Compliant Pb-free H L W 0.85 7.0

Contextual Info: 19-2538; Rev 0; 7/02 1:9 Differential LVPECL/LVECL/HSTL Clock and Data Driver Features ♦ 50ps max Output-to-Output Skew ♦ 1.5psRMS (max) Random Jitter ♦ Guaranteed 300mV Differential Output at 1.0GHz ♦ +2.375V to +3.8V Supplies for Differential HSTL/LVPECL

Contextual Info: MOTOROLA Order this document by MC10EP89/D SEMICONDUCTOR TECHNICAL DATA Product Preview M C10EP89 Coaxial Cable Driver The MC10EP89 is a differential fanout gate specifically designed to drive coaxial cables. The device is especially useful in digital video

SY89831U

Abstract: SY89830U SY89831UMG SY89831UMGTR SY89831UMI SY89831UMITR
Contextual Info: ULTRA-PRECISION 1:4 LVPECL FANOUT BUFFER/TRANSLATOR WITH INTERNAL TERMINATION Micrel, Inc. Precision Edge ® SY89831U Precision Edge SY89831U FEATURES Precision Edge® „ Guaranteed AC performance over temperature and voltage: • DC-to > 2.0GHz throughput

SN75LVDS81

Abstract: DS90C383A DS90C383AMTD DS90CF383A DS90CF383AMTD DS90CF384 SN75LVDS83
Contextual Info: DS90C383A/DS90CF383A +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display FPD Link-65 MHz +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 1.0 General Description 2.0 Features The DS90C383A/DS90CF383A transmitter converts 28 bits

Contextual Info: SN65LVDS306 www.ti.com SLLS765B – SEPTEMBER 2006 – REVISED FEBRUARY 2007 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER FEATURES • • • • • • • • • • • • Serial Interface Technology Compatible With FlatLink 3G Such as SN65LVDS305