2 INPUT OR GATE ECL FAMILY Search Results

F100102DC

Contextual Info: F100102 Quint 2-Input OR/NOR Gate F100K ECL Product Connection Diagrams Description The F100102 is a monolithic quint 2-input OR/NOR gate with common enable. Ail inputs have 50 kO pull-down resistors and all outputs are buffered. Pin Names Dna- Dne E O a-O e

MC10H104

Abstract: MC10H107
Contextual Info: ECL 10KH High-Speed Emitter-Coupled Logic Family M C 1 0 H 1 0 4 /M C I OH107 Quad 2-Input AND Gate/TViple 2-Input Exclusive OR/NOR Gate Features/B enefits Ordering Information • Propagation delay, 1 ns typical PART NUMBER PACKAGE TEMPERATURE MC10H104 MC10H107

MC100E104

Abstract: MC10E104 MC10E104FN transistor j 127 ECL IC NAND
Contextual Info: MC10E104, MC100E104 5V ECL Quint 2-Input AND/NAND Gate Description The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

ECL IC NAND

Contextual Info: MC10E104, MC100E104 5V ECL Quint 2-Input AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

MC10H118

Abstract: nl 545
Contextual Info: ECL 10KH High-Speed Emitter Coupled Logic Family MC10H118 Dual 2-W ide 3-Input OR-AND Gate Ordering Information Features/Benefits • Propagation delay 1 ns typical PART NUMBER PACKAGE TEMPERATURE MC10H118 J,N,NL 20 Com • Power dissipation, 100 mW/Gate typical

IC of XNOR GATE

Abstract: MC100E107 MC10E107 MC10E107FN
Contextual Info: MC10E107, MC100E107 5V ECL Quint 2-Input XOR/XNOR Gate Description The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are

nl 545

Abstract: MC10H117
Contextual Info: ECL 10KH High-Speed Em itter-Coupled Logic Fam ily M C10H117 Dual 2-W ide 2 -3 Input OR-AND/OR-AND-INVERT Gate Features/ Benefits Ordering Inform ation • Propagation delay 1 ns typical PART NUMBER PACKAGE TEMPERATURE MC10H117 J,N,NL 20 Com • Power dissipation, 100 mW/gate typical

ECL10KH

Abstract: MC10H103 2 input or gate ecl family
Contextual Info: ECL 10KH High-Speed Em itter-Coupled Logic Fam ily M C10H103 Quad 2-Input OR Gate Features/B enefits Ordering Inform ation • Propagation delay, 1.0 ns typical PART NUMBER • Power dissipation 25 mW/gate PACKAGE TEMPERATURE J,N,NL 20 Com MC10H103 • Noise margin 150 mV

aoo8

Abstract: smd ic lv 1116 ao65 Tolerance limit for basic dimensions in ansi y14
Contextual Info: < Military 10H518 M O T O R O LA Dual 2-Wide 3-Input “OR-AND” Gate ELECTRICALLY TESTED PER: 5962-8755901 The 10H518 is a basic logic building block providing the OR/AND function, use­ ful in data control and digital multiplexing applications. This M ECL 10H part is a functional/pinout duplication of the standard M ECL

on222 transistor

Contextual Info: SEMICONDUCTOR CORPORATION Data Sheet High Performance FX Family Gate Arrays FX Family Features • 20,000-350,000 Raw Gates, Channelless Array Architecture • Sea-of-Gates Architecture and Four Layer Metal for High Density • Array Performance - Typical gate delay: 97 ps @ 0.19 mW

VIPER IC

Abstract: viper 17 L viper gate control circuits OAI221 VIPer Design Software internal structure of ic 741 on222 transistor ic 741 comparator signal generator OA4444 VIPER
Contextual Info: SEMICONDUCTOR CORPORATION Data Sheet Hjgh Performance¡ Low Cosí Viper Family Viper Family Gate Arrays Features • 7,000-13,000 Usable Gates, Channelless Array Architecture • Industry Standard Plastic Packaging • Superior Speed/Power Performance and Cost

HLP5

Abstract: full adder using x-OR and NAND gate OAI221 OA41 G5108
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Data Sheet High Performance SCFUDCFL Gate Arrays SCFX Family Features • Tailored Specifically for High Performance Telecommunications and Data Communica­ tions Applications. 2.5 GHz Performance. Phase-Locked Loop Megacells Available:

ET3000

Abstract: ER22T m21g ET-30 R04T ET1500 ECL IC NAND IR1P
Contextual Info: FUJITSU MICROELECTRONICS 31E D 374T7Í35 001MbIO 3 E B FMI February 1990 Edition 1.1 FUJITSU DATA S H E E T ET750, ET1500, ET3000, ET4500 ECL Series Gate Arrays_ D E S C R IP T IO N The Fujitsu ET series gate array family Is a group of high-speed gate arrays with

HALF ADDER 74

Abstract: half adder ttl 8 bit half adder 74 mb53030 ECL NAND IMPLEMENTATION HALF ADDER Unbuffered LFP4 LDR3
Contextual Info: * * c P September 1990 Edition 2.0 FUJITSU DATA SH EET MB53xxx FURY uSeries GaAs Gate Arrays The Fujitsu FURY gate array series incorporates Fujitsu’s 0.8-micron GaAs self-aligned gate process to produce a family of devices ideally suited to the highest performance applications. Incorporating very

SH100E

Abstract: siemens SH100E elxr siemens Nand gate SH100E5 TRANSISTOR K 2191
Contextual Info: 7 1991 SIEMENS ASIC Product Description SH100E ECL/CML Gale Amy Family FEATURES • Gate complexities from 1,500 to 16,000 gates ■ 120 ps gate delay, 90 ps differential • 1.5 GHz D flip-flop, 1.7 GHz differential ■ Both ECL and CML macro families ■ TTL I/O available

T12B1

Abstract: h607 H603 1803e H606 H600 H604 MC10H600 BF 273 transistor h601
Contextual Info: AN1402/D MC10/100H640 Translator Family I/O SPICE Modeling Kit Prepared by: Debbie Beckwith ECL Applications Engineering http://onsemi.com APPLICATION NOTE structure, respectively. Six different output buffers represent all of the output buffers for the H60x series of translators.

Contextual Info: AT&T Preliminary Data Sheet ATE2000 Series Gate Array Description The ATE2000 High-Speed Gate Array is a member of the customized TTL-ECL gate array family and is designed using advanced Scaled Fast Oxide Isolated Logic SFOXIL Bipolar technology. The device

H604

Abstract: FPS001 IBM POS power supply schematics AN1402 h607 H600 H606 MC10H600 H603 h601 transistor
Contextual Info: AN1402 Application Note MC10/100H600 Translator Family I/O SPICE Modeling Kit Prepared by Debbie Beckwith ECL Applications Engineering This application note provides the SPICE information necessary to accurately model system interconnect situations for designs which utilize the translator circuits

74l85

Contextual Info: JANUARY 1995 ULA DX Series DS3746 -1.2 ULA DX SERIES HIGH PERFORMANCE MIXED SIGNAL ARRAY FAMILY COMBINING ENHANCED ANALOG PERFORMANCE WITH ULTRA HIGH DIGITAL SPEEDS The DX series of arrays exploits the features of the latest LK complementary bipolar process, whose

OA2222L

Abstract: XN2222 025x
Contextual Info: SEMICONDUCTOR CORPORATION Data Sheet High Performance GLX Family Low Power GaAs Gate Arrays Features • Sea-of-Gates Core Low-Power Macros Available • Five Array Sizes: 15K, 40K, 80K, 120K and 220K Raw Gates Standard TTL, LVTTL, ECL, LVPECL, GTL, HSTL and LVDS I/O Compatibility

Contextual Info: H OlM EYüJELL/SS ELEK-, M IL 03 D Ë| 4551Ö72 DDGG3].t □ T -9 2 -//-Û 7 Honeywell Radiation Hardened Bipolar Gate Array Family " Preliminary HM3500R, HVM10000R Family Features • Strategic Radiation Hardness Allows Spaced Based System Operations • Broad Performance Optimized Family Allows Flexible

DV46 1

Contextual Info: JANUARY 1995 ULA DT/DV Series DS2468 -2.2 ULA DT & DV SERIES HIGH PERFORMANCE MIXED DIGITAL/ANALOG ARRAY FAMILY ULTRA HIGH SPEED DIGITAL ARRAYS WITH HIGH PERFORMANCE ANALOG The DT/DV series of arrays are designed to provide cost effective single chip solutions to high speed

Contextual Info: DATA SHEET =AT bT Bipolar Gate Arrays TE1000 Series Gate Array DESCRIPTION CAD FEATURES The TE1000 high-speed gate array is a member o f the Customized TTL-E C L Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 1000 internal gates and has a total of 96 inputs,

1N3064

Abstract: 1N916 TE1000 TE3000
Contextual Info: DATA SHEET Bipolar Gate Arrays TE1000 Series Gate Array DESCRIPTION The TE1000 high-speed gate array is a member o f the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 1000 internal gates and has a total of 96 inputs,