1CL1 Search Results

74HC4096

Abstract: EQUIVALENT TIMER IC WITH CD 4060 rs flip-flop IC 7400 C4050A shiftregister PIPO C148A LS 7476 L1AA C4051A LS294
Contextual Info: Selection Guide C2MOS Logic TC74HC/HCT Series 2. High Speed CMOS Selection Guide GATE NAND HCOOA NOR AND OR INVERTER, BUFFER EXCLUSIVE OR/NOR SC HM ITT TRIGGER HC02A HC08A H C31A H C04A H C86A H C14A H C51A H C4049A M ULTI FUNCTION LEVEL SHIFTER HCTOOA HCT02A

LXXXXXXXX

Abstract: TNC 24 mk 2 026R CY7C09569V tb136 A14L CY7C09579V
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -• -■ -■ -^ jjÉBT *¿f5’00“’ '*'^ 7“T ■ ■ ■ ■ <1; .r {• o CY7C09569V CY7C09579V PRELIMINARY f:,ò b 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM • 3.3V Low o p e ratin g p ow er

Contextual Info: 3.3 V CMOS 16-BIT BUSTRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP,

Contextual Info: 3.3V CMOS 16-BIT BUS BUSTRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH162245 DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: GEC PLESSEY S I- M ] . ( \ I) 1J (. T O K 54HSC/T Series Radiation Hard High Speed CMOS/SOS Logic S S10504FSF Issue 1.4 N ovem ber 1990 Gates and Buffers Features 54H SC/T00 54HSC/T02 54HSC/T04 54HSC/T08 54HSC/T10 54H SC/T14 54HSC/T21 54HSC/T27 5 4 H SO T 3 2

82801 SCHEMATIC DIAGRAM

Abstract: 5-101 pong rn isa io MIPI ISP Intel MIPI DSI spec ac9721 intel AF 82801 82801 g SCHEMATIC DIAGRAM it313 sch 5127
Contextual Info: intef i 82801AA ICH and Intet 82801AB (ICHO) I/O Controller Hub Datasheet A p r ii 1 9 9 9 O rder N um ber: 2^06 ^5-0 01 in Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

Contextual Info: HARRIS SENICOND SECTOR 37E » M3GSS71 0Q213bl 0 1 E 13547 3875081 G E SOLID STATE T IHAS T-46-07-08 CD4013A Types Dual 'D’-Type Flip-Flop Voo 1“ The R CA-C D 4013A consists o f tw o identical. Independent data-type flip -flo p s. Each flip flo p has independent data, set, reset, and

FOR1B

Contextual Info: EM47CM1688SBB1 1 Revision1History1 1 Revision10.11 Jun.12012 1 -First1release.1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Jun.120121 1/381 www.eorex.com1 1 EM47CM1688SBB1 1 1Gb1(8Mx8Bank×16)1Double1DATA1RATE131SDRAM1

YEW-2575

Contextual Info: POWER TYPE MOS MOSX EU RoHS 小形酸化金属皮膜固定抵抗器 Fixed Metal Oxide Film Resistors Small type 小形金属皮膜固定抵抗器 Fixed Metal Film Resistors (Small type) •構造図 Construction C ② ③ ④ ⑤ φd ① ⑥ L 外装色：ラベンダー Coating color： Lavender

CQ 419

Abstract: oms 450 ifr mosfet 2SK2165-01 SC-65 2SK2165
Contextual Info: 2SK2165-01 FUJI PO W ER M O S-F E T N-CHANNEL SILICON POWER MOS-FET FAP-IIIA SERIES • Features Outline Drawings • Hiiih current • Low on-resistance • No secondary breakdown • Low driving power • Hicjh forward Transconductance • Avalanche-proof

dq35j

Abstract: Nippon capacitors
Contextual Info: MM2M0J32L / MM2M0J36L CMOS 2M x 32bit / 36bit Fast Page Mode Memory Module DESCRIPTION The MM1M0J32L/J36L is a 64 Megabit Dynamic Random Access Memory Module organized as 2,097,152 x 32 x 36 bits in a 72 lead single inline module. The module contains sixteen 1M x 4bit Dynamic Random Access

Contextual Info: bEE » MOSEL-VITELIC MOSEL- VITELIC • baSBB^l DDGSOSb 170 ■ MOVI V53C404F HIGH PERFORMANCE, LOW POWER 1 M X 4 BIT FAST PAGE MODE CMOS D YNAMIC RAM H IG H P E R F O R M A N C E V 5 3 C 4 0 4 F Max. RAS Access Time, tRAf. PRELIMINARY 6 0 /6 0 L 7 0 /7 0 L

3502M

Abstract: 3tb52 M188A m184a
Contextual Info: FJUL63182A-02 ＭＳＭ６３１８２Ａ／１８４Ａ／１８８Ａ ユーザーズマニュアル 第 2 版 2001 年 12 月 10 日 4 FJUL63182A-02 ご 注 意 １． 本書に記載された内容は製品改善および技術改良等により将来予告なしに変更することがありま

Contextual Info: HD66214T M icro-TA B (80-Channel Colum n Driver in M icro -T C P ) Description Features The H D66214T, the colum n driver for a large liquid crystal graphic display, features as many as 80 LCD outputs pow ered by 80 internal LCD drive circuits. This device latches 4-bit parallel

DH311

Abstract: V53C100FK
Contextual Info: M O S E L V IT E L IC V53C1 OOF FAMILY HIGH PERFORMANCE, LOW POWER 1M X 1 BIT FAST PAGE MODE CMOS DYNAMIC RAM 60/60L 70/70L 80/80L Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA) 30 ns 35 ns 40 ns Max. CAS Access Time, (tCAC)

Contextual Info: 3.3V CMOS 16-BIT TRANS­ PARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: IDT74ALVCH162373 larly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When

NN5118160A

Abstract: NN5118160B WA137
Contextual Info: NN5118160A / NN5118160B series Fast Page Mode CMOS 1Mx 16bit Dynamic RAM NPN a DESCRIPTION The NN5118160A / NN5118160B series is a high performance CMOS Dynamic Random Access Memory organized as 1,048,576 words by 16 bits. The NN5118160A / B series is fabricated with advanced CMOS technology and designed with

Contextual Info: M O S EL V IT E L IC V53C 16258H 2 5 6 K X 16 P A G E M O D E C M O S D Y N A M IC R A M W ITH E X T E N D E D D A TA O U T P U T HIGH PERFORMANCE P R E LIM IN A R Y 45 50 55 60 Max. RAS Access Time, tRAc 45 ns 50 ns 55 ns 60 ns Max. Column Address Access Time, (tCAA)

nn5117405

Contextual Info: NN5116405B / NN5117405B series EDO Hyper Page Mode CMOS 4M x 4bit Dynamic RAM NPN>a( DESCRIPTION The NN5116405B / NN5117405B series is a high performance CMOS Dynamic Random Access Memory organized as 4,194,304 words by 4-bits. The NN5116405B / NN5117405B series is fabricated with advanced CMOS technology and de­

t3d43

Abstract: m184a T2D7 SEMI XXHX E10HZ PCF 7951 3502m TB 1275 N DATA SHEET 12-12B EASE63180
Contextual Info: お客様各位 資料中の「沖電気」「ＯＫＩ」等名称の OKI セミコンダクタ株式会社への変更について 2008 年 10 月 1 日を以って沖電気工業株式会社の半導体事業は OKI セミコン ダクタ株式会社に承継されました。 従いまして、本資料中には「沖電気工業株

V53C1625BH

Contextual Info: M O SEL V IT E U C V53C16258H 256K X 16 PAG E MODE CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT HIGH PERFORMANCE PRELIMINARY 45 50 55 60 Max. RAS Access Time, tRAC 45 ns 50 ns 55 ns 60 ns Max. Column Address Access Time, Ocaa) 22 ns 25 ns 28 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (tPC)

Contextual Info: 3.3V CMOS 16-BIT BUS BUSTRANSCEIVER WITH 3-STATE OUTPUTS DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP,

Contextual Info: 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP,

Contextual Info: 3.3V CMOS 16-BIT EDGETRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH16374 DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)