ALVCH16374 Search Results

Contextual Info: 3.3V CMOS 16-BIT REGISTER ALVCH16374 IDT74ALVCH162374 IDT74ALVC16374 ADVANCE INFORMATION FEATURES: DESCRIPTION: • Common features: The ALVCH16374 16-bit edge-triggered D-type registers are built using advanced dual metal CMOS technology. These high-speed, low-power registers are ideal for use as buffer

74ALVCH16374

Abstract: 74ALVCH16374T MTD48
Contextual Info: Revised February 2002 ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold General Description Features The ALVCH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and output enable (OE) are common to

74ALVCH16374

Abstract: 74ALVCH16374T MTD48
Contextual Info: Revised September 2001 ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold General Description Features The ALVCH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and output enable (OE) are common to

74ALVCH16374

Abstract: 74ALVCH16374GX 74ALVCH16374MTD MO-205 MTD48
Contextual Info: Revised September 2001 ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold General Description Features The ALVCH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and output enable (OE) are common to

Contextual Info: www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus Family Operates From 1.65 to 3.6 V Max tpd of 4.2 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

ALVC16374

Abstract: IDT74ALVCH162374 IDT74ALVCH16374
Contextual Info: 3.3V CMOS 16-BIT REGISTER ALVCH16374 IDT74ALVCH162374 IDT74ALVC16374 ADVANCE INFORMATION Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Common features: – 0.5 MICRON CMOS Technology – Typical tSK o (Output Skew) < 250ps – ESD > 2000V per MIL-STD-883, Method 3015;

Contextual Info: 3.3V CMOS 16-BIT EDGETRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021F – JULY 1995 – REVISED NOVEMBER 2000 D D D D Member of Texas Instruments’ Widebus  Family DGG OR DL PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17

A115-A

Abstract: SN74ALVCH16374 SN74ALVCH16374DL SN74ALVCH16374DLR
Contextual Info: ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021H – JULY 1995 – REVISED MAY 2002 D D D D DGG OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus  Family Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown

Contextual Info: www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus Family Operates From 1.65 to 3.6 V Max tpd of 4.2 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

74LVC05

Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed

7054F

Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
Contextual Info: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver

A115-A

Abstract: SN74ALVCH16374 SN74ALVCH16374DL SN74ALVCH16374DLR
Contextual Info: ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021I – JULY 1995 – REVISED SEPTEMBER 2003 D D D D D D D DGG OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus  Family Operates From 1.65 V to 3.6 V Max tpd of 4.2 ns at 3.3 V

d742

Contextual Info: FEA TU RES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP, and 0.40mm pitch TVSOP packages Extended commercial range of - 40°C to + 85°C

IDT74ALVCH16374

Abstract: alvch16374
Contextual Info: ALVCH16374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE ALVCH16374 3.3V CMOS 16-BIT EDGETRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD DESCRIPTION: FEATURES: This 16-bit edge-triggered D-type flip-flop is built using advanced dual

Contextual Info: www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus Family Operates From 1.65 to 3.6 V Max tpd of 4.2 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

Contextual Info: 3.3V CMOS 16-BIT EDGETRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FE A T U R E S : - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 0.635mm pitch SSOP, 0.50mm pitch TSSOP,

Contextual Info: www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus Family Operates From 1.65 to 3.6 V Max tpd of 4.2 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

Contextual Info: ALVCH16374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ALVCH16374 3.3V CMOS 16-BIT EDGETRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology

Contextual Info: 3.3V CMOS 16-BIT EDGETRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD ALVCH16374 DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus Family Operates From 1.65 to 3.6 V Max tpd of 4.2 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

Contextual Info: www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus Family Operates From 1.65 to 3.6 V Max tpd of 4.2 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

A115-A

Abstract: SN74ALVCH16374 SN74ALVCH16374DL SN74ALVCH16374DLR
Contextual Info: ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021H – JULY 1995 – REVISED MAY 2002 D D D D DGG OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus  Family Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown

Contextual Info: www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus Family Operates From 1.65 to 3.6 V Max tpd of 4.2 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors