16STATE Search Results

8280 counter

Abstract: 8280A 8280
Contextual Info: 8280-A,F,W • 8281-A,F,W PIN CONFIGURATION DESCRIPTION The 8280 Decade Counter and 8281 16State Binary Counter are four-bit subsys­ tems providing a wide variety of counter/storage register applications with a minimum number of packages. The 8280 Decade Counter can be con­

rneg2

Contextual Info: QT1F-Plus Device Quad T1 Framer-Plus TXC-03103C DESCRIPTION • D4 SF, ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1 gapped clock • Monitor function for frame pulse, clock and data

Contextual Info: TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP CONTROLLERS SPRS094E – APRIL 1999 – REVISED AUGUST 2000 D High-Performance Static CMOS Technology D D D D D External Memory Interface LF2407 – 33-ns Instruction Cycle Time (30 MHz) – 30 MIPS Performance

Contextual Info: TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors Data Manual Literature Number: SPRS174N April 2001 − Revised May 2006 PRODUCTION DATA information is current as of publication date. Products conform to

Contextual Info: TMS320F2808, TMS320F2806 TMS320F2801, UCD9501 Digital Signal Processors Data Manual Literature Number: SPRS230F October 2003 – Revised September 2005 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

SPRC081

Abstract: 100Ball
Contextual Info: TMS320F2808, TMS320F2806 TMS320F2801, UCD9501 Digital Signal Processors Data Manual Literature Number: SPRS230F October 2003 – Revised September 2005 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

transistor C2810

Contextual Info: SM320F2810-EP, SM320F2811-EP, SM320F2812-EP SM320C2810-EP, SM320C2811-EP, SM320C2812-EP Digital Signal Processors Data Manual Literature Number: SGUS051A March 2004 − Revised October 2004 This document contains information on products in more than one phase of

m1 250c fuse

Abstract: at32uc3c em 234 stepper dtx 370 DTH block diagram lta 301 VT 546 Modem basic circuit diagram EIC 4021 shift registers 4050
Contextual Info: Features • High Performance, Low Power 32-bit AVR Microcontroller – – – – • • • • • • • • • • • • Compact Single-cycle RISC Instruction Set Including DSP Instruction Set Built-in Floating-Point Processing Unit FPU Read-Modify-Write Instructions and Atomic Bit Manipulation

f2407

Abstract: TMS320LC2402A TMS320LC2403A TMS320LC2404A TMS320LC2406A TMS320LF2402A TMS320LF2403A TMS320LF2406A TMS320LF2407A TMS320LF2407A CPU and Instruction Set
Contextual Info: TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 D High-Performance Static CMOS Technology D External Memory Interface LF2407A

TMS320f2812 pwm vector code c

Abstract: PWM by using dsp F2812 TMS320F2811 SVPWM 2812 external adc to tms320f2812 tms320f2812 program capture example TMS320F2812 processor manual TMS320C2811 TMS320C2812 TMS320F2810
Contextual Info: TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not

ATMEGA32U4

Abstract: 7766D atmega16 assembly IC ATMEGA16 power supply schematic ATmega16 IR remote control 7766E SP12 SP13 SP14 SP15
Contextual Info: Features • High Performance, Low Power AVR 8-Bit Microcontroller • Advanced RISC Architecture • • • • – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

16mb HIGH-SPEED ASYNCHRONOUS SRAM

Abstract: IBM041816CHLBC IBM043616CHLBC SA37T
Contextual Info: . IBM043616CHLBC IBM041816CHLBC 16Mb 512K x 36 & 1M x 18 SRAM Features • 512K x 36 or 1M x 18 organization • Registered addresses, controls, and data-ins • CMOS technology • Burst mode of operation • Double-data-rate and single-data-rate synchronous mode of operation

A65H73361

Abstract: A65H83181 SA10 SA11 SA12 SA13 SA15
Contextual Info: A65H73361/A65H83181 Series 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Preliminary Document Title 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Revision History Rev. No. 2.0 PRELIMINARY

SA37T

Abstract: cq 721 IBM041816CBLBC IBM043616CBLBC
Contextual Info: . IBM043616CBLBC IBM041816CBLBC 16Mb 512K x 36 & 1M x 18 SRAM Features • 512K x 36 or 1M x 18 organization • Registered addresses, controls, and data-ins • CMOS technology • Burst mode of operation • Double-data-rate and single-data-rate synchronous mode of operation

K7Z327285M

Contextual Info: K7Z327285M Preliminary 512Kx72 DLW Double Late Write RAM Document Title 512Kx72 DLW(Double Late Write) RAM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial document. 1. Device name change from Double Late Write SigmaRAM to Double Late Write RAM

IBM0418A41NLAB

Abstract: IBM0418A81NLAB IBM0436A41NLAB IBM0436A81NLAB
Contextual Info: IBM0436A41NLAB IBM0418A41NLAB IBM0418A81NLAB IBM0436A81NLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM . Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • Registered outputs • 30 Ω drivers

AN6019

Abstract: PAC10 1GM1
Contextual Info: ispPAC 10 Features Functional Block Diagram • IN-SYSTEM PROGRAMMABLE ISP ANALOG CIRCUIT — Four Instrument Amplifier Gain/Attenuation Stages — Signal Summation (Up to 4 Inputs) — Precision Active Filtering (10kHz to 100kHz) — No External Components Needed for Configuration

IS61QDB22M36

Abstract: D0-35 IS61QDB24M18
Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Two echo clocks (CQ and CQ) that are delivered

IS61DDB21M36

Abstract: 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI
Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . I May 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

D0-35

Abstract: IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3
Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 4) Synchronous SRAMs 7 Q . May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.

AN6027

Abstract: AN6026 151m75
Contextual Info: In-System Programmable Analog Circuit October 2002 Data Sheet Features Functional Block Diagram • Flexible Interface and Programming Control • • • • Full configuration capability, SPI or JTAG modes Unlimited device updates using SRAM register E2CMOS for non-volatile configuration storage

IS61QDB41M36

Abstract: 61QDB41M36 IS61QDB41M36-250M3L D0-35 IS61QDB41M36-250M3 IS61QDB42M18
Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . I April 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.

10D-11

Abstract: K7R160982B K7R160982B-FC16 K7R160982B-FC20 K7R161882B K7R161882B-FC16 K7R161882B-FC20 K7R163682B K7R163682B-FC16 K7R163682B-FC20
Contextual Info: K7R163682B K7R161882B K7R160982B 512Kx36 & 1Mx18 & 2Mx9 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002 Advance 0.1 1. Change the Boundary scan exit order.

MOTOROLA ONCORE UT plus

Abstract: hp 35821 6132 RAM 731 motorola MPCPRGREF/D LG E50 MPC8xx QMC SMC microcode MPC857DSL MPC857T MPC862
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MPC862UM/D 09/2002, REV 2 MPC862 PowerQUICC Family User’s Manual Supports MPC862P MPC862T MPC857T MPC857DSL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.