16 MACROCELL Search Results

4-bit even parity using mux 8-1

Abstract: full subtractor implementation using NOR gate 4096 bit RAM 74 full subtractor full subtractor using mux
Contextual Info: Introduction to Delta39K’s Carry Chain Introduction VCC VCC GCLK[3:0] Logic Block PIM 16 16 Logic Block PIM 39 39 Logic Block PIM 16 16 Logic Block PIM 39 39 Logic Block PIM 16 16 Logic Block PIM 39 39 Logic Block PIM 16 16 Logic Block PIM 39 23 Cluster Memory PIM

EP600

Abstract: 5c060 P5C060-55 intel PLD EP600 programming D5C060-45
Contextual Info: in t e i 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 16 Macrocells with Programmable I/O Architecture; up to 20 Inputs 4 Dedicated, 16 I/O or 16 Outputs ■ Programmable Output Registers can be

vhdl code for 8-bit serial adder

Abstract: dse1 D950-CORE ieee floating point alu in vhdl vhdl code for 16 bit barrel shift register vhdl code for 8-bit adder
Contextual Info: D950-CORE 16-Bit Fixed Point Digital Signal Processor DSP Core • ■ ■ ■ ■ OUTPUT CLOCKS 16 XA-bus 16 YA-bus 16 CALCULATION 16 UNIT PROGRAM CONTROL UNIT 3 ID-bus 16 IA-bus 16 DATA MEMORY 6 ADDRESS PROGRAM MEMORY ■ UNIT VDD VSS ■ DATA CALCULATION

8 bit barrel shifter vhdl code

Abstract: vhdl code for 8-bit serial adder D950-CORE vhdl code for SIGNED MULTIPLIER accumulator vhdl code for 8-bit adder Ya14
Contextual Info: D950-CORE 16-Bit Fixed Point Digital Signal Processor DSP Core • ■ ■ ■ ■ OUTPUT CLOCKS 6 16 XA-bus 16 YA-bus 16 CALCULATION 16 UNIT PROGRAM CONTROL UNIT 3 ID-bus 16 IA-bus 16 DATA MEMORY ADDRESS PROGRAM MEMORY ■ UNIT VDD VSS ■ DATA CALCULATION

39a132

Abstract: d950 BSU60 vhdl code lte vhdl code for SIGNED MULTIPLIER accumulator D950CORE D950-CORE 4 bit barrel shifter using mux YA11 vhdl code for 16 bit barrel shifter
Contextual Info: D950-CORE 16-BIT FIXED POINT DIGITAL SIGNAL PROCESSOR DSP CORE PRODUCT PREVIEW • ■ ■ ■ ■ ■ ADDRESS OUTPUT CLOCKS 6 16 XA-bus 16 CALCULATION 16 UNIT YA-bus PROGRAM CONTROL UNIT 16 3 ID-bus IA-bus 16 16 DATA MEMORY YD-bus XD-bus UNIT VDD VSS ■

4512c

Abstract: ispMACH lc4064v LC4032 LC4032V-10TN48I 4032V 4000ZC LC4384V-35TN176C LC4512V-5FN256I LC4128V-5T128C LC4512V
Contextual Info: Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 16 16 Generic Logic Block 36 I/O Block ORP 16 36 16 16 36 36 Generic 16 Logic Block VCCO1 GND TCK TMS TDI TDO VCC GND GOE0 GOE1 16 I/O Bank 0 ORP Generic Logic Block I/O Block ORP I/O Bank 1 I/O Block

ARM processor

Abstract: ARM processor fundamentals ARM processor pin configuration ARM7500 LA-1931 la1628 BD 176
Contextual Info: 1 16 11 Clocks, Power Saving, and Reset 16.1 Clock control 16-2 16.2 Power management 16-3 16.3 Reset 16-6 ARM7500 Data Sheet ARM DDI 0050C Preliminary - Unrestricted This chapter describes clock control, power management, and reset. 16-1 Clocks, Power Saving, and Reset

Contextual Info: EP600 EPLD t i d = n & 16-Macrocell Device \ June 1993, ver. 1 Data Sheet Supplement 16-macrocell Classic EPLD - Combinatorial speeds with tPD = 45 ns Counter frequencies up to 222 MHz Pipelined data rates up to 263 MHz □ Programmable I/O architecture with up to 20 inputs or 16 outputs

ARM7500FE

Abstract: ARM FPA DRAM Controller 08FF
Contextual Info: 1 11 Memory and I/O Programmers’ Model 16 This chapter details the programmable registers for the memory and I/O subsystem. 16.1 Introduction 16-2 16.2 Summary of Registers 16-2 16.3 Register Description 16-6 ARM7500FE Data Sheet ARM DDI 0077B Open Access - Preliminary

Contextual Info: UM10524 LPC1315/16/17/45/46/47 User manual Rev. 4 — 12 March 2013 User manual Document information Info Content Keywords LPC1315/16/17/45/46/47, ARM Cortex-M3, microcontroller, USB Abstract LPC1315/16/17/45/46/47 User manual UM10524 NXP Semiconductors LPC1315/16/17/45/46/47 User manual

80c196 application note

Contextual Info: PSD4235G2V Flash in-system programmable ISP peripherals for 16-bit MCUs (3.3 V supply) Features PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/Os: • ■ 64 Kbit SRAM ■ PLD with macrocells

Contextual Info: - tB i 3 1992 EP600-45 High-Performance 16-Macrocell EPLD Data Sheet June 1991, ver. 1 Features □ □ □ □ □ □ General Description High-performance 16-macrocell Classic EPLD Combinatorial speeds with tFD = 45 ns Counter frequencies up to 22.2 MHz

Contextual Info: % Micro Linear FB300 Tile Arrav Family Description FB324 Bipolar Tile Array The FB324 has 6 general purpose tiles and 16 high performance tiles. The six general purpose tiles can use any of the predefined macrocells from the FB300 family. The 16 high performance tiles support higher

AMD 685

Abstract: cascode transistor array 5K02 tiles ecl 10K signetics FB300 FB324
Contextual Info: 1%, Micro Linear FB324 BIPOLAR TILE ARRAY FB300 Tile Arrav Family Description The FB324 has 6 general purpose tiles and 16 high performance tiles. The six general purpose tiles can use any of the predefined macrocells from the FB300 family. The 16 high performance tiles support higher

EP600

Abstract: EP600 eprom 5c060 P5C060-45 EP600 programming 5C060-55 5C06055 EP6003 16-MACROCELL 74HC
Contextual Info: intJ. 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 8 P-Terms, Selectable SOP Invert, Clear and OE P-Terms for Each Macrocell ■ 16 Macrocells with Programmable I/O

Contextual Info: EP610 EPLD Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins

Contextual Info: LPC2420/2460 Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 6.2 — 16 October 2013 Product data sheet 1. General description NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bit

Contextual Info: EP610A EPLD AN b r ^ n ^ \ High-Performance 16-Macrocell Device March 1993, ver. 2 Data Sheet Supplement □ Features □ □ □ P re lim in a ry Inform ation □ □ □ □ □ □ Highest-performance 16-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns

LPC2000

Abstract: LPC2468 LPC2468FBD208 LPC2468FET208 LQFP208 TFBGA208
Contextual Info: LPC2468 Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 02 — 16 October 2007 Preliminary data sheet 1. General description NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bit

ALTERA EP610

Abstract: MIL-STD-883-compliant
Contextual Info: EP610 MIL-STD-883-Compliant EPLD Features □ □ □ □ □ □ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD = 35 ns Counter frequencies up to 28.5 MHz Pipelined data rates up to 37 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs

Multiplexers

Abstract: 5C060 5C060-55 EP600 programming 5C060-45 EP600 P5C060-55 intel PLD
Contextual Info: in t e i. 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 8 P-Terms, Selectable SOP Invert, Clear and OE P-Terms for Each Macrocell ■ 16 Macrocells with Programmable I/O

fxz 556

Abstract: EP6101-10 EP610 pipelined adder EP610-Z5 EP610-30 EP610-35 EP610-25 EP610-15 EP610-20
Contextual Info: EP6 1 0 EPLD High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins

EP610

Abstract: MIL-STD-883-compliant TI EP610 EP610-15 PALCE610 altera ep610 ALTERA MAX 5000 programming EP610-20 EP610I
Contextual Info: EP610 EPLD Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with t PD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 Clock pins

EP61Q-15

Abstract: EP61B EP610-30 EP610-35 EP610-25 EP610 EP610-15 EP610-20 EP6101-10 EP610I
Contextual Info: EP610 EPLD Features • ■ ■ ■ ■ ■ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs