EP6003 Search Results

EP600

Abstract: altera ep320 altera EP600 ep600i EP600 eprom ep800 EP600 programming EP6001
Contextual Info: A N b r~ & €P600 D v A '' n !A ERASABLE p r o g r a m m a b l e L O G IC DEVICE FEATURES GENERAL DESCRIPTION • H igh density over 600 gates replacem ent fo r T TL and 74HC. • Advanced CH M O S EPROM technology, allows erase and reprogram. • High speed, tpd = 25 ns.

Multiplexers

Abstract: 5C060 5C060-55 EP600 programming 5C060-45 EP600 P5C060-55 intel PLD
Contextual Info: in t e i. 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 8 P-Terms, Selectable SOP Invert, Clear and OE P-Terms for Each Macrocell ■ 16 Macrocells with Programmable I/O

EP600 programming

Abstract: EP600 EP610 "pin compatible" 74HC EP610 CE-P600 EP6003 16 macrocells altera EP600
Contextual Info: ie «A C RO CELL EPLD EP600 FEATURES GEN ERAL DESCRIPTION • High density log ic replacem ent for T T L and 74HC. • Functional and pin com patible with the Altera EP600. • High speed, tpd = 45 ns. • Asynchronous clocking of all registers or banked register operation from 2 synchronous clocks.

EP600

Abstract: 5c060 P5C060-55 intel PLD EP600 programming D5C060-45
Contextual Info: in t e i 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 16 Macrocells with Programmable I/O Architecture; up to 20 Inputs 4 Dedicated, 16 I/O or 16 Outputs ■ Programmable Output Registers can be

Contextual Info: - tB i 3 1992 EP600-45 High-Performance 16-Macrocell EPLD Data Sheet June 1991, ver. 1 Features □ □ □ □ □ □ General Description High-performance 16-macrocell Classic EPLD Combinatorial speeds with tFD = 45 ns Counter frequencies up to 22.2 MHz

Contextual Info: EP600 EPLD t i d = n & 16-Macrocell Device \ June 1993, ver. 1 Data Sheet Supplement 16-macrocell Classic EPLD - Combinatorial speeds with tPD = 45 ns Counter frequencies up to 222 MHz Pipelined data rates up to 263 MHz □ Programmable I/O architecture with up to 20 inputs or 16 outputs

EP600

Abstract: EP600 eprom 5c060 P5C060-45 EP600 programming 5C060-55 5C06055 EP6003 16-MACROCELL 74HC
Contextual Info: intJ. 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 8 P-Terms, Selectable SOP Invert, Clear and OE P-Terms for Each Macrocell ■ 16 Macrocells with Programmable I/O

altera EP600

Abstract: ep800 EP600 EP600 programming EP610 "pin compatible" EP610 74HC GOG111S 16 macrocells 05T5372
Contextual Info: ALTERA CORP 24E D 05^5372 0001113 5 rr-tUrG-iFi iu I m m m :.SSI6-M ACROCELL EPLD FEATURES GENERAL DESCRIPTION • High density logic replacement for TTL and 74HC. • Functional and pin compatible with the Altera EP600. • High speed, tpd = 45 ns. • Asynchronous clocking of ail registers or banked