EP600 Search Results

Contextual Info: Ml intpl 6 1992 ÌPLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tpo 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Extensive Software and Programming Support via Intel and Third Party Tools

PLD610-10

Abstract: 85C060 D610 p EP610 "pin compatible" PLD610
Contextual Info: PLD610 PRELIMINARY CYPRESS SEMICONDUCTOR Multipurpose BiCMOS PLD Function, pin, and JEDEC compatible with EP600, EP610, EP630,85C060, and PALCE610 PLDs Very high performance — tpo = 10 ns 16 I/O macrocells, each having: — Choice of combinatorial or regis­

D85C060-25

Abstract: PLD610 85C060 P85C060-25 PLD610-25 P85C060-15 D85C060-10 intel 85C060 n85c060 pld610-15
Contextual Info: intel ¡PLD610/85C060 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610, 85C060 and 5C060 PLDs • tpD 10 ns, 100 M H z C o u n te r F req u en cy w /ln te rn a l F e e d b a c k ■ E xte n s ive S o ftw a re an d P ro g ram m in g

EP600 programming

Abstract: ple3-12a Altera EP1800 EPS448 PLE3-12 EP610 ORDERING ep1800 EP600 altera ep900 PLED448
Contextual Info: PLED/J/G P L 1 D /J/G PROGRAMMING ADAPTORS PLED/J/G FEATURES GENERAL DESCRIPTION • Programming adaptors for Altera EPS448, EP600/ EP610, EP900/EP910, EP1210, EPB1400 and EP1800/ EP1810 EPLDs. The Altera PLED/J/G 448, 600, 900, 1210, 1400 and 1800 are enhancement products allowing device pro­

npld610

Abstract: NPLD610-10 PALCE610 EP610 ORDERING PLD610 DPLD610-25 intel 85C060 85C060 TNPLD610 intel PLD
Contextual Info: in tj ¡PLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDa • * m - m r ' "< ^ . *. » • tpQ 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Ice = 105 m A max-@ 1 MHz

sts37e

Abstract: EP600IPC-45 EP600IDC-45 EP600IPC-55 altera ep610 5c060 EP600IDM883B55 ep600ilc ep600i EP600IDC45
Contextual Info: EP600I Classic EPLD Data Sheet Supplement March 1995, ver. 2 This data sheet supplement should be used together with the Classic Family Data Sheet and the Altera Device Package Outlines Data Sheet in the current data book. Features ^ □ □ □ □ □ Formerly Intel's 5C060 device

DPLD610-15

Abstract: npld610 iPLD610 PPLD610-25 PPLD610 TNPLD610 DPLD610-10 intel 85C060 NPLD610-10 PLD610
Contextual Info: in t e i ÌPLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Com patible wKh EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDa • tpQ 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Ice = 105 mA max- @ 1 MHz ■ Programmable Low-Power Option for

d6105

Contextual Info: PLD610 PRELIMINARY OYPRESS SEMICONDUCTOR • Function, pin, and JEDEC compatible with EP600, EP610, EP630,85C060, and PALCE610 PLDs • Veiy high performance — tpo = 10 ns • 16 I/O macrocells, each having: — Choice of combinatorial or regis­ tered output

EP600 programming

Abstract: EP600 EP610 "pin compatible" 74HC EP610 CE-P600 EP6003 16 macrocells altera EP600
Contextual Info: ie «A C RO CELL EPLD EP600 FEATURES GEN ERAL DESCRIPTION • High density log ic replacem ent for T T L and 74HC. • Functional and pin com patible with the Altera EP600. • High speed, tpd = 45 ns. • Asynchronous clocking of all registers or banked register operation from 2 synchronous clocks.

of 16450 UART

Abstract: EP600 uart 16450 timing design of UART 16550 uart timing EP600 programming 16450
Contextual Info: Eureka Technology EP600 UART Product Summary FEATURES • Functionally compatible with 16550. • Supports Character 16450 and FIFO (16550) mode operations. • Designed optimized for ASIC and PLD implementations. • Synchronous design with edge triggered flip-flops based on system clock input.

Contextual Info: intel MILITARY ¡PLD610 16-MACROCELL CHMOS juPLD Function, Pin, and JEDEC Compatible with 5C060, EP600, EP610, EP630 and CE630 PLDs Programmable Clock System with 2 Synchronous Clocks and Asynchro­ nous Clocking Option on all Registers tpD 15 ns, 66 MHz Counter Frequency

EP600IPC-45

Abstract: 5962-8686401la ep600i Altera Classic EPLDs altera ep610
Contextual Info: ANbi^n^ EP600I Classic EPLD Data Sheet Supplement March 1995, ver. 2 This data sheet supplement should be used together with the Classic Family Data Sheet and the Altera Device Package Outlines Data Sheet in the current data book. Features ^ □ □ □ □

P85C060-25

Abstract: D85C060 PLD610-25 D85C060-25 intel 85C060 D85C060-15 IPLD610-15 EP610 ORDERING p85c060 N85C060-12
Contextual Info: INTEL CORP tIEMORY/PLD/ in t e l SbE D • HfiSblTb D077infl fl3£ ^p ÌPLD610/85C060 FAST 16-MACROCELL CMOS PLD h ITL2 ^ '^ - o 0 Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs ■ tpo 10 ns, 100 MHz Counter Frequency

Contextual Info: - tB i 3 1992 EP600-45 High-Performance 16-Macrocell EPLD Data Sheet June 1991, ver. 1 Features □ □ □ □ □ □ General Description High-performance 16-macrocell Classic EPLD Combinatorial speeds with tFD = 45 ns Counter frequencies up to 22.2 MHz

Contextual Info: EP600 EPLD t i d = n & 16-Macrocell Device \ June 1993, ver. 1 Data Sheet Supplement 16-macrocell Classic EPLD - Combinatorial speeds with tPD = 45 ns Counter frequencies up to 222 MHz Pipelined data rates up to 263 MHz □ Programmable I/O architecture with up to 20 inputs or 16 outputs

Contextual Info: intei’ pm M85C060 600-GATE CHMOS 16-MACROCELL EPLD High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, 54HC SSI and MSI Logic, and PLDs Programmable Output Registers; Can be Configured as D, T, SR, or JK Types High-Speed Upgrade to EP600, EP610

85c060

Abstract: intel iPLD610 pld610 P85C060-25 D85C060-15 EP610 ORDERING intel 85C060 intel PLD 29045 EP610 "pin compatible"
Contextual Info: in tJ . ¡PLD610/85C060 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tPD 10 ns, 100 MHz C ounter Frequency w /ln tern al Feedback ■ Extensive Softw are and Programming

altera EP600

Abstract: ep800 EP600 EP600 programming EP610 "pin compatible" EP610 74HC GOG111S 16 macrocells 05T5372
Contextual Info: ALTERA CORP 24E D 05^5372 0001113 5 rr-tUrG-iFi iu I m m m :.SSI6-M ACROCELL EPLD FEATURES GENERAL DESCRIPTION • High density logic replacement for TTL and 74HC. • Functional and pin compatible with the Altera EP600. • High speed, tpd = 45 ns. • Asynchronous clocking of ail registers or banked

programming manual EPLD

Abstract: EP320 EP600 programming EP600 programmer manual EPLD programmer schematic ep320 programmer EPLD PLE3-12 program altera ep320 EPLD
Contextual Info: HARDWARE P ro g ra m m e r In te rfa c e • EPLD M aster Program ming Unit PLE3-12 per­ mits direct program m ing of A ltera PE3XX 20 Pin & EP12XX (40 Pin) devices. • Two sam ple EPLDs fo r evaluation EP600). (EP320, • PLED600 Programming adaptor.

DPLD610-15

Abstract: PLD610-10 PLD610 DPLD610-25 EP610 ORDERING intel 85C060 intel PLD TNPLD610 2164 intel 85C060
Contextual Info: in tj ¡PLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tpo 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Icc = 1 0 5 mA max. @ 1 MHz ■ Programmable Low-Power Option for

EP320DM

Abstract: EP600DM883B EPM5128GM883B EP320DM883B EP1800GM883B EP1800GM ep310dm883b EP600DM EP910dm EP1810GM883B
Contextual Info: Military Products / A 1 b Data Sheet September 1991, ver. 2 In trO d U C tiO n T ab les 1 throu gh 7 p ro v id e inform ation on m ilitary-tem p eratu re-ran g e, M I L - S T D - 8 8 3 B - q u a l i f i e d , a n d D E S C i l’ L D s. F o r d e t a ile d i n f o r m a t i o n , re fe r

ep610

Abstract: EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP610I P6101
Contextual Info: EP610EPLD Features H igh -perform an ce, 16-m acrocell Classic EPLD C om binatorial speeds w ith as low as 10 ns C oun ter frequencies of up to 100 M H z Pipelined d ata rates of up to 125 M H z Program m able I / O arch itectu re w ith up to 20 inputs o r 16 ou tp uts

ABEL-HDL Reference Manual

Abstract: blown fuse indicator project report ABEL Design Manual power inverter circuit diagram schematics vector E0600 EP600 P16R4 P22V10 P18CV8
Contextual Info: ABEL Design Product Overviews Manual You are here Programmable IC Entry Manual Synario ECS and Board Entry Manual Schematic and Board Tools Manual ABEL Design Manual April 1997 Synario Design Automation, a division of Data I/O, has made every attempt to ensure that the information in this document is accurate and complete. Synario

XC3030-70PC84C

Abstract: EPM5128LC EP330PC-15 A1020 transistor A1010B-PL68C EPM5128GM EP330PC15 EP330PC XC3042-70PC84C A1020A-PL84C
Contextual Info: ULCt Cross-Reference Matra MHS Cross reference list of devices supported for ULC conversion is not exhaustiv as new devices are added regularly. Additional devices not shown in this list, may also be supported. MHS encourages you to contact your local TEMIC sales representative