D950CORE Search Results

i80188

Abstract: transistor AN132 I8031 Architecture of TMS320C4X QUALCOMM Reference design AT89Sxxx block diagram of of TMS320C4X GSM qualcomm GSM-Chipset INSTRUCTION SET of TMS320C4X
Contextual Info: Serial Memory Interfaces: Trends and Options Application Note June 7, 2005 AN132.0 Author: Carlos Martinez Introduction The Emergence of Serial Memories In the dynamic semiconductor industry, conventions taken for gospel today are heresy tomorrow. In one of these classic

D950

Abstract: D952 ST18952 Ya13 SCR SN 102 YBs 70 YA11
Contextual Info: ST18952 DIGITAL SIGNAL PROCESSOR DSP CHIP PRELIMINARY DATA • ■ ■ Programmable D950 Core ■ Data calculation unit ■ Address calculation unit ■ Program control unit ■ Fast and flexible buses ■ 66MIPS - 15 ns instruction cycle time 16.5 Kwords data memory (RAM)

PIR CONTROLLER LP 0001

Abstract: ED-9P PDCR 912 pdcr 921 23D31 D950 D950CORE ST18-AU1 dialnorm dynamic range dsei 17-12
Contextual Info: ST18-AU1 SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER PRELIMINARY DATA FEATURES • ■ ■ ■ Single chip multi-function audio decoder able to decompress DOLBY AC-3, MPEG-1 and MPEG-2 audio streams. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Emulation unit and TAP

vhdl code for 8-bit serial adder

Abstract: dse1 D950-CORE ieee floating point alu in vhdl vhdl code for 16 bit barrel shift register vhdl code for 8-bit adder
Contextual Info: D950-CORE 16-Bit Fixed Point Digital Signal Processor DSP Core • ■ ■ ■ ■ OUTPUT CLOCKS 16 XA-bus 16 YA-bus 16 CALCULATION 16 UNIT PROGRAM CONTROL UNIT 3 ID-bus 16 IA-bus 16 DATA MEMORY 6 ADDRESS PROGRAM MEMORY ■ UNIT VDD VSS ■ DATA CALCULATION

vd950

Contextual Info: D950-CORE Preliminary Specification January 1995 This is Preliminary Data from SGS-THOMSON. Details are subject to change without notice. USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORISED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

Contextual Info: n = T S G S -IH O M S O N ">Ji» [MI»i[LiÊiniB R!lDÊê ST 18952 DIGITAL SIGNAL P R O C ESSO R DSP) CHIP P R ELIM IN A R Y DATA • Programmable D950 Core ■ Data calculation unit ■ Address calculation unit ■ Program control unit ■ Fast and flexible buses

8 bit barrel shifter vhdl code

Abstract: vhdl code for 8-bit serial adder D950-CORE vhdl code for SIGNED MULTIPLIER accumulator vhdl code for 8-bit adder Ya14
Contextual Info: D950-CORE 16-Bit Fixed Point Digital Signal Processor DSP Core • ■ ■ ■ ■ OUTPUT CLOCKS 6 16 XA-bus 16 YA-bus 16 CALCULATION 16 UNIT PROGRAM CONTROL UNIT 3 ID-bus 16 IA-bus 16 DATA MEMORY ADDRESS PROGRAM MEMORY ■ UNIT VDD VSS ■ DATA CALCULATION

transistor AN132

Abstract: i80188 Plessey an132 I8031 DCAM101 DSP16xx SH70xx AT89Sxxx 68HC11 AN132
Contextual Info: Application Note AN132 Serial Memory Interfaces: Trends and Options by Carlos Martinez, November 1999 Introduction Memory Density In the dynamic semiconductor industry, conventions taken for gospel today are heresy tomorrow. In one of these classic battlegrounds, parallel busses, once

d950

Abstract: vero 16 PIN PIR controller IC PINOUT D952 ST18952 scr tag 89 TAG 8704 60T15 YA14 IMO7
Contextual Info: . SGS-THOMSON k jÆ ST18952 , DIGITAL SIGNAL P R O C ESSO R DSP CHIP PR ELIM IN A R Y DATA Programmable D950 Core • ■ ■ ■ ■ Data calculation unit Address calculation unit Program control unit Fast and flexible buses 66MIPS -1 5 ns instruction cycle time

16 bit single cycle mips vhdl

Abstract: vhdl code for 8 bit barrel shifter vhdl code for 16 bit dsp processor CODE VHDL TO ISA BUS INTERFACE verilog code for 16 bit barrel shifter d950 vhdl code for 4 bit barrel shifter ieee floating point multiplier vhdl powerful ieee floating point vhdl
Contextual Info: D950 DSP CORE presentation V1.02 - August 1999 EMBEDDED DSP CORE APPROACH D950-DSP MAIN FEATURES OVERVIEW D950-DSP TARGET APPLICATIONS APPLICATION SOFTWARE D950 HARDWARE DESIGN KIT DELIVERABLES D950 DEVELOPMENT TOOLSET CUSTOMER SUPPORT D950 DSP core presentation - August 1999 - file: d950mkt1.pre

ip611

Contextual Info: D 9 5 Q -C O R E Preliminary Specification January 1995 This is Preliminary Data from SGS-THOMSON. Details are subject to change without notice. USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORISED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

Contextual Info: r=Z SGS-THOMSON ST18952 DIGITAL SIGNAL P R O C E SSO R DSP CHIP PR E LIM IN A R Y DATA • Programmable D950 Core ■ Data calculation unit ■ Address calculation unit ■ Program control unit 16.5 Kwords data memory TAP ■ Fast and flexible buses ■ 66MIPS - 1 5 ns instruction cycle time

Contextual Info: SGS-THOMSON ilUHgüMMÊi D950-CQRE 16-Bit Fixed Point Digital Signal Processor DSP Core PRELIMINARY DATA P erform ance • 66 Mips - 15ns instruction cycle time M em ory O rgan izatio n ■ HARVARD architecture ■ Two 64k x 16-bit data memory spaces ■ One 64k x 16-bit program memory space

D950-CORE

Abstract: IMSA110 ST18 PQFP144
Contextual Info: PROCESSORS & PERIPHERALS DIGITAL SIGNAL PROCESSORS ST18 FAMILY The D950-CORE is a general purpose programmable 16-bit fixed point Digital Signal Processor DSP Core. The D950-CORE can be embedded as a megafunction in a gate array or cell-based device through the combination of

t0440

Abstract: PIR CONTROLLER LP 0001 D950-DSP
Contextual Info: C T ^ 7 / S G S -T H O M S O N S T 1 8 -A U 1 SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER PRELIMINARY DATA FEATURES • Single chip multi-function audio decoder able to decompress DOLBY AC-3, MPEG-1 and MPEG-2 audio streams. ■ Maximum 5.1 channel DOLBY AC-3 decoding