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Contextual Info: PAL22V10C _ PAL22VP10C Universal PAL Device SEMICONDUCTOR Features • • Ultra high speed supports today’s and tomorrow’s fastest microprocessors 10 user>programmable output macrocells — Output polarity control — Registered or combinatorial

Contextual Info: CY7B180 CY7B181 PRELIMINARY CYPRESS SEMICONDUCTOR Features 4K x 18 Cache Tag • Can be used as 4K x 18 SRAM Functional Description Supports 50-MHz cache for all major high-speed processors 4K x 18 tag organization BiCMOS for optimum speed/power High speed

L22V10C-10PC

Contextual Info: PAL22V10C PAL22VP10C y CYPRESS Universal PAL Device B iC M O S process and Ti-W fuses, the PAL22V10C and PAL22VP10C use the fam iliarsum -of-products A N D -O R logic structure and a new concept, the program ­ m able m acrocell. • 10 user-programmable output

E13 TIW

Contextual Info: PR ELIM INARY CYPRESS SEMICONDUCTOR • Generic 24-Pin PAL Device 10 user-programmable output macrocells U sing BiCM O S process and Ti-W fuses, the P L D 20G 10C im plem ents the fam iliar sum -of-products A N D -O R logic struc­ ture. It provides 12 dedicated input pins

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpD = 7.5 ns — tsi = 3 ns — fMAX = 105MHz • Reduced ground bounce and under­ shoot • PLCC and LCC packages with addi­ tional V cc and Vss pins for lowest

PAL22V10C-7JC

Abstract: 22V10C 22V10C-10 CERAMIC LEADLESS CHIP CARRIER PAL22V10C-10JC K73 Package PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC PAL22V10C10DC PAL22V10C7JC PAL22VP10C-10JC
Contextual Info: PAL22V10C PAL22VP10C CYPRESS • 10 user-programmable output macrocells — Output polarity control — Registered or combinatorial operation — 2 new feedback paths PAL22VP10C • Synchronous PRESET, asynchronous RESET, and PRELOAD capability for flexible design and testability

10DC IR 3 PINS

Contextual Info: PAL22V10C PAL22VP10C CYPRESS SEMICONDUCTOR • Ultra high speed supports today's and tomorrow's fastest microprocessors — tp j * user-programmable output macrocells — Output polarity control BiCMOS process and Ti-W fuses, the PAL22V10C and PAL22VP10C use the

Contextual Info: Revision: Monday, January 4,1993 IM « •_ r «-ar CY7C373 PRELIMINARY CYPRESS = :~ ;r " SEMICONDUCTOR 64-Macrocell Flash PLD performance of the 22V10 to high-density PLDs. The 64 macrocells in the CY7C373 are di­ vided between four logicblocks. Each logic

22V10C

Abstract: PAL22V10C-7DC
Contextual Info: — . _ PAL22V10C _ PAL22VP10C SEMICONDUCTOR Features • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpD = 6 ns — tsu = 3 ns — fMAX = 117 MHz • Reduced ground bounce and under­ shoot • PLCC and LCC packages with addi­

PAL22

Contextual Info: PAL22V10C PAL22VP10C CYPRESS SEMICONDUCTOR Universal PAL Device BiCMOS process and Ti-W fuses, the PAL22V10C and PAL22VP10C use the familiar sum-of-products AND-OR log­ ic structure and a new concept, the pro­ grammable macrocell. • 10 user-programmable output

Contextual Info: 7C373: Thursday, September 24,1992 Revision: Monday, January 4,1993 I MAR 2 3 1983 CY7C374 p r e l im in a r y S jS ry p p F ^ q — . 11 •■■ • 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 dock pins • No hidden delays