12YMB Search Results

Contextual Info: PRELIMINARY '# CYPRESS 32Kx 18 Synchronous Cache RAM Features • Direct interface with the processor and external cache controller • Supports 66-MHz Pentium micro­ processor cache systems with zero wait states • Asynchronous output enable • I/Os capable o f 3.3V operation

Contextual Info: PAL22V10C _ PAL22VP10C Universal PAL Device SEMICONDUCTOR Features • • Ultra high speed supports today’s and tomorrow’s fastest microprocessors 10 user>programmable output macrocells — Output polarity control — Registered or combinatorial

EQUIVALENT cd 1031 cs

Abstract: 7C1031
Contextual Info: CY7C1031 CY7C1032 PRELIM INARY 64K x 18 Synchronous Cache RAM • Direct interface with the processor and external cache controller • Asynchronous output enable • VOs capable of 33V operation • JEDEC-standard pinout • 52-pin PLCC and PQFP packaging

CY7C178

Abstract: CY7C179 AL4A
Contextual Info: PRELIMINARY '# CYPRESS 32Kx 18 Synchronous Cache RAM Features • Direct interface with the processor and external cache controller • Supports 66-MHz Pentium micro­ processor cache systems with zero wait states • Asynchronous output enable • I/Os capable o f 3.3V operation

80486 microprocessor block diagram and pin diagrams

Abstract: 80486 microprocessor block diagram and pin diagram r2868 EQUIVALENT cd 1031 intel 80486 CY7C1031 CY7C1032 80486 microprocessor 80486 microprocessor pin out diagram
Contextual Info: 1CY 7C10 32 CY7C1031 CY7C1032 PRELIMINARY 64K x 18 Synchronous Cache RAM Features Functional Description • Supports 66-MHz Pentium microprocessor cache systems with zero wait states • 64K by 18 common I/O • Fast clock-to-output times — 8.5 ns • Two-bit wraparound counter supporting Pentium microprocessor and 486 burst sequence 7C1031

ADVM

Abstract: cy7c379 CY7C178 CY7C179 RD7I141
Contextual Info: PRELIMINARY CYPRESS Features • Supports 66-MHzPentium micro­ processor cache systems with zero wait states • 32K by 18 common I/O • Fast clock-to-output times — 8.5 ns • Itoo-bit wraparound counter support­ ing Pentium and 486 burst sequence

L22V10C-10PC

Contextual Info: PAL22V10C PAL22VP10C y CYPRESS Universal PAL Device B iC M O S process and Ti-W fuses, the PAL22V10C and PAL22VP10C use the fam iliarsum -of-products A N D -O R logic structure and a new concept, the program ­ m able m acrocell. • 10 user-programmable output

Contextual Info: ^ CY7C1031 CY7C1032 PRELIMINARY 5"s s CYPRESS *^ SEMICONDUCTOR Features ~ • Direct interface with the processor and external cache controller • Supports 66-MHz Pentium micro­ processor cache systems with zero wait states • 1/Os capable o f 3.3V operation

Contextual Info: PRELIMINARY CYPRESS 64K x 18 Synchronous Cache RAM F eatu res • Direct interface with the processor and external cache controller • Supports 66'MHz Pentium 'Mmicro­ processor cache systems with zero wait states • Asynchronous output enable • 1/Os capable of 3.3V operation

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpD = 7.5 ns — tsi = 3 ns — fMAX = 105MHz • Reduced ground bounce and under­ shoot • PLCC and LCC packages with addi­ tional V cc and Vss pins for lowest

PAL22V10C-7JC

Abstract: 22V10C 22V10C-10 CERAMIC LEADLESS CHIP CARRIER PAL22V10C-10JC K73 Package PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC PAL22V10C10DC PAL22V10C7JC PAL22VP10C-10JC
Contextual Info: PAL22V10C PAL22VP10C CYPRESS • 10 user-programmable output macrocells — Output polarity control — Registered or combinatorial operation — 2 new feedback paths PAL22VP10C • Synchronous PRESET, asynchronous RESET, and PRELOAD capability for flexible design and testability

10DC IR 3 PINS

Contextual Info: PAL22V10C PAL22VP10C CYPRESS SEMICONDUCTOR • Ultra high speed supports today's and tomorrow's fastest microprocessors — tp j * user-programmable output macrocells — Output polarity control BiCMOS process and Ti-W fuses, the PAL22V10C and PAL22VP10C use the

22V10C

Abstract: PAL22V10C-7DC
Contextual Info: — . _ PAL22V10C _ PAL22VP10C SEMICONDUCTOR Features • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpD = 6 ns — tsu = 3 ns — fMAX = 117 MHz • Reduced ground bounce and under­ shoot • PLCC and LCC packages with addi­

PAL22

Contextual Info: PAL22V10C PAL22VP10C CYPRESS SEMICONDUCTOR Universal PAL Device BiCMOS process and Ti-W fuses, the PAL22V10C and PAL22VP10C use the familiar sum-of-products AND-OR log­ ic structure and a new concept, the pro­ grammable macrocell. • 10 user-programmable output