149L Search Results

LTP14058AC

Abstract: Ap1780 LTP-14058 ELTP1 LTP14158 LTP-14158
Contextual Info: i TP 1405ffA/ 14158A L 1 F "148^A /149l8A A LITEM fl 30 5x8 SINGLE COLOR & MULTICOLOR DOT MATRIX LED DISPLAYS FEATURES • 1 4 IN C H 3 5 7 6 m m M A T R I X H E I G H T • LO W POW ER R EQ U IR EM ENT • H IG H C O N T R A S T • H IG H B R I G H T N E S S

Contextual Info: SIEMENS Silicon PIN Photodiode Daylight Filter Dimensions in inches mm ; (35 5) .020 (.5) 1.317(33.5) .100 (254) j J_ , Cathode 1 .206(5.1) .181 (4.6) f-r .031 (.8) .016 (.4) ,.071 (1.8) rt)47(1.2) ,283 (7.2) .259(6.6) .043(1.1) .028(0.7) FEATURES • Especially suitable for application* of

Contextual Info: QL3012 / QL3 0 1 2 R 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA . 12,000 usable PLD gates, 118 I/O pins 11,520 bit RAM Option E High Performance and High Density -12,000 Usable PLD Gates with 118 I/Os

CH341A

Abstract: digital trainer schematic diagram laf 0001 CH3401 J0123 ccs ldl HP 3D6 000A75 X77H-X70H TO SI 788 48D
Contextual Info: H i/1 I - = - ^ • QE1F Device Quad E1 Framer TXC-03104 DATA SHEET FEATURES DESCRIPTION • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and

Contextual Info: DATA SHEET ÌÀTCT Bipolar Gate Arrays TE3000 Series Gate Array DESCRIPTION CAD FEATURES The TE3000 high-speed gate array is a member of the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 3000 internal gates and has a total o f 168 inputs,

ET3000

Abstract: ER22T m21g ET-30 R04T ET1500 ECL IC NAND IR1P
Contextual Info: FUJITSU MICROELECTRONICS 31E D 374T7Í35 001MbIO 3 E B FMI February 1990 Edition 1.1 FUJITSU DATA S H E E T ET750, ET1500, ET3000, ET4500 ECL Series Gate Arrays_ D E S C R IP T IO N The Fujitsu ET series gate array family Is a group of high-speed gate arrays with

1N3064

Abstract: 1N916 TE1000 TE3000
Contextual Info: DATA SHEET ÌAT&T Bipolar Gate Arrays TE3000 Series Gate Array DESCRIPTION CAD FEATURES The TE3000 high-speed gate array is a member of the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 3000 internal gates and has a total o f 168 inputs,

1265R

Abstract: Sony CXD ICX038BNB 149L
Contextual Info: SONY CXD1265R CCD Camera Timing Generator Description The CXD1265R generates the timing pulses required by the CCD image sensors as well as signal processing circuits. Features • NTSC and PAL compatible • Compatible with digital and analog camera systems

IEEE-1296

Abstract: BA017 BA011 271091 M82389 D1301S Multibus ii protocol 176526 BA022 BAD29
Contextual Info: in te i M82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER M ilita ry Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

ET3004M

Abstract: CS31E 4input nor gate ET-3004M
Contextual Info: FUJITSU MICROELECTRONICS 31E D • 374^7^2 D014b2b 7 ■ F M I cP February 1990 Edition 1.1 - FUJITSU D A TA S H EE T ET2004M, ET2009M, ET3004M ET-M Series Gate Arrays DESCRIPTION The Fujitsu ET-M Series of ECL Gate Arrays are designed to provide both fast ECL

BA021

Contextual Info: M82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER Military u Highly Integrated VLSI Device • High Performance Coprocessing Functions — Offloads CPU for Communication and Bus Interfacing — 40 Megabytes/Sec Burst Transfer Speed

PEF 24628

Abstract: PSB 21493 siemens PMB 6610 47n60c3 psb 21553 Pmb7725 PEF 22628 PMB6610 psb 50505 PMB 6819
Contextual Info: 2006/2007 Published by Infineon Technologies AG Ordering No. B192-H6780-G10-X-7600 Printed in Germany PS 080648. nb Infineon Product Catalog for Distribution 2006/2007 Product Catalog for Distribution www.infineon.com/distribution Edition July 2006 Published by

BCM 4336

Abstract: 2A0565 C2335 2A280Z C1740 bipolar transistor transistor A1267 a1273 transistor c2335 r 2B0565 2b265
Contextual Info: 01.07.2005 11:10 Uhr Seite 2 Shor t Form Catalog for Distribution 2005/06 w w w. i n f i n e o n . c o m / d i s t r i b u t i o n Published by Infineon Technologies AG Ordering No. B192-H6780-G9-X-7600 Printed in Germany LM 060550. Shor t Form Catalog Distribution 2005/06

pin diagrams of basic gates

Abstract: 100-PIN 84-PIN PL84 QL2003 QL2003-1PF100C QL2003-1PF144C QL2003-1PL84C
Contextual Info: QL2003 3,000 Gate 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility PRELIM INARY DA TA pASIC 2 HIGHLIGHTS Rev. B 5 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance