136Q Search Results

Contextual Info: UNCONTROLLED DOCUMENT PART NUMBER SC:0.25 REV. S S F - L X H 136QSOC PRELIMINARY IN P / N 3.60 [0.142] MAX. 4.60 [0.181] 4.60 [0.181: 02,90 [00,114] ELECTRO-OPTICAL CHARACTERISTICS Ta =25'C -I- 0,50 [0,0201 PARAMETER MIN PEAK WAVELENGTH 8.60 [0.339: o 6.35 [0.250]

CY101E383

Abstract: diode SKE 39
Contextual Info: W r CY10E383 CY101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • B iC M O S for optim um speed/power • H igh speed max. — 2.5 n s Ipu TTL-to-EC L — 3.5 n s tpo EC L-to-TTL The CY10/101E383 is a new-generation

Contextual Info: 7 PLD20G10C C YPRESS • Features • Ultra high speed supports today’s and tomorrow’s fastest microprocessors Generic 24-Pin PAL Device 10 user-programmable output macrocells — Output polarity control — Registered or combinatorial operation — tpo = 7.5 ns

Contextual Info: UltraLogic 128-Macrocell Flash CPLD is designed to bring th e ease o f use and high perform ance o f th e 22V10 to highdensity CPLDs. Features • 128 macrocells in eight logic blocks • 64 I/O pins T he 128 m acrocells in th e CY7C374 are di­ vided betw een eight logic blocks. Each

Contextual Info: CY7C372 PRELIMINARY CYPRESS SEMICONDUCTOR 64-Macrocell Flash PLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed The CY7C372 is a Flash Erasable Pro­

Contextual Info: w ~ CYPRESS Features • 32 macrocells in two logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • In-System Reprogrammable ISR Flash technology — JTAG interface • No hidden delays • High speed — f M A X = 143 MHz — tpD= 8*5 ns

319S2

Contextual Info: WFw CYPRESS CY7C374Ì ADVANCED INFORMATION UltraLogic 128-Macrocell Flash CPLD Features • 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR™ Flash technology — JTAG interface

Contextual Info: 32-Macrocell Flash CPLD Features Functional Description • 32 macrocells in two logic blocks The CY7C371 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the F lash370 ” family of highdensity, high-speed CPLDs. Like all mem­

Contextual Info: y PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpo = 15 ns, tco — 10 ns, ts = 12 ns — Military: tpo = 20 ns, tco = 15 ns, ts = 15 ns • Low power — Ice max.: 70 mA, commercial — Ice max.: 100 mA, military • Commercial and military temperature

22V10G-7

Contextual Info: m f CYPRESS Features — f[HAX = 1 6 6 MHz External • Reduced ground bounce and under­ shoot • PLCC and LCC packages w ith addi­ tional Vc c and V ss pins for lowest ground bounce • Up to 22 inputs and 10 outputs for more logic power Synchronous PRESET, asynchronous

C1573

Abstract: sim 300
Contextual Info: Miuiouay, úo^ioiiiuvi tn, 199& Revision: Tuesday, December 22,1992 •fi»«* n i W «! S7E D 5 5 5 ^ 2 C YP RE S S SEMI CONDUCTOR ODDTOMl ICYP 3bl CY7C375 PRELIMINARY CYPRESS SEMICONDUCTOR 128-Macrocell FLASH PLD Features Functional Description • 128 macroceils in eight logic blocks

37-25615

Abstract: CY37256 CY37256P160-125UMB
Contextual Info: UltraLogic 256-Macrocell ISR™ CPLD Features — tCo = 4 -5 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 256 macrocells in sixteen logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os

CY37512

Contextual Info: UltraLogic 512-Macrocell ISR™ CPLD Features — tco = 6 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os

961.114

Contextual Info: T Product r num ber 3.5 70232-XYY REF. 11 REF. DIM A + 0.1 - i 11.85 DIM C WIN. REQUIRED PC BOARD 17.1 REF REF. U\YOUT CO MPONENT SIDE NOTES: 1 FOR DIM A, B AND C S E E DRAWING 70232 SH EET 2 AND UP FOR OTHER LOADING CONFIGURATIONS S E E DRAWING 85713

Contextual Info: CY7C372 PRELIMINARY CYPRESS 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed — fMAX - 125 MHz — tpD - 10 ns

lmw14

Contextual Info: PLDC20G10B/PLDC20Gt0 i f C Y PR ESS CMOS Generic 24-Pin Reprogrammable Logic Device F ea tu res • Fast — C om m ercial: Ip» = 15 n s, t o = 10 n s, l s = 12 ns — M ilitary: tpu = 20 n s, t( <> = *5 n s, ts = 15 ns • G eneric arch itectu re to replace sta n ­

tlO41

Abstract: 7C373-125 CY7C373 CY7C374 FLASH370 Wo2c
Contextual Info: CYPRESS Features • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — f M A X = 12S MHz — tpo = 10 ns — ts = 5.5 ns — tc o = 6-5 ns • Electrically alterable Flash

12L10

Abstract: 16L6 18L4 20L10 20L8
Contextual Info: PLD20G10C i f CYPR ESS Features • 10 user-programmable output macrocells — Output polarity control — Registered or combinatorial operation — Pin or product term output enable control • Ultra high speed supports today’s and tomorrow’s fastest microprocessors

Contextual Info: 7C372: Wednesday, September 23,1992 Revision: Monday, January 4,1993 57E D m 550*^2 SbO CYPRESS SEMICONDUCTOR 'T 'A í - ñ - o i CY7C372 PRELIMINARY «sar CYPRESS . SEMICONDUCTOR ICYP 64-Macrocell Flash PLD Features Functional Description • 64 macrocells in four logic blocks

logic block diagram of cypress flash 370 device

Abstract: cypress flash 370 device SEM03 features cypress flash 370 7C371-2
Contextual Info: 7C373: Thursday, September 24,1992 .Revision: Monday,January4,1993 S7E D • 2 5 f l T L > t iE 00CH031 41E CYPRESS SEMICONDUCTOR ^ ^ s ts s s s 'Z ^ ^ i is m = ^ 'T'^' ci- PRELIMINARY Q Y PR ESS . • 128 macrocells in eight logic blocks

L22V10C-10PC

Contextual Info: PAL22V10C PAL22VP10C y CYPRESS Universal PAL Device B iC M O S process and Ti-W fuses, the PAL22V10C and PAL22VP10C use the fam iliarsum -of-products A N D -O R logic structure and a new concept, the program ­ m able m acrocell. • 10 user-programmable output

Contextual Info: '= CYPRESS CY7C372 UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed - f M A X = 125 MHz The CY7C372 is a Flash erasable Complex

Contextual Info: CYPRESS UltraLogic 64-Macrocell Flash CPLD Device CPLD and is p art of the F lash37<M™ family of high-density, high­ speed CPLDs. Like all members of the F lash37(M family, the CY7C372i is de­ signed to bring the ease of use and high performance of the 22V10, as well as PCI

Contextual Info: CY7C372 PRELIMINARY WFJ CYPRESS 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • Highspeed — fMAX = 125 MHz — tpD = 10 ns