LASH370 Search Results

Contextual Info: 32-Macrocell Flash CPLD Features Functional Description • 32 macrocells in two logic blocks The CY7C371 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the F lash370 ” family of highdensity, high-speed CPLDs. Like all mem­

1N5817

Abstract: 1N5818 IRF7201 LT1013 LT1301 MAX761 MIC3172 SC1628
Contextual Info: LASH370i 5V to 12V DC-DC Converter Solutions This application note provides various solutions for the 12V supervoltage requirement for our flash-based In-System Reprogrammable CPLDs in designs that do not already include a source for 12V. When a single F LASH370i component is in a programming

cypress 22V10

Abstract: 22V10 CY7C373 CY7C374 FLASH370
Contextual Info: fax id: 6128 For new designs see CY7C373i CY7C373 UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks The CY7C373 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the F LASH370TM family of

361125

Abstract: CY7C361
Contextual Info: This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. For new designs, please refer to the F lash370 family CYPRESS Features Ultra High Speed State Machine EPLD T he CY7C361 is a C M O S erasable, p ro ­ gram m able logic device E P L D with very

cypress flash 370

Abstract: logic block diagram of cypress flash 370 device 22v10 CY7C375 FLASH370 o112i cypress flash 370 CPLD cypress flash 370 device technology
Contextual Info: fax id: 6130 For new designs see CY7C375i CY7C375 UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 28 macrocells in eight logic blocks • 28 I/O pins • 6 dedicated inputs including 4 clock pins • Bus Hold capabilities on all I/Os and dedicated inputs

Contextual Info: CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins

74151

Abstract: 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer
Contextual Info: 1CY 7C34 0 fax id: 6100 EPL D Family CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDS Features tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. • Erasable, user-configurable CMOS EPLDs capable of

CY7C373

Abstract: CY7C374 FLASH370
Contextual Info: For new designs see CY7C373i CY7C373 UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks The CY7C373 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the LASH370TM family of

FLASH370I

Abstract: ORCAD CY3140 CY3144 vector generator PLD386 Cypress Programmable Logic schematic sim vhdl code for 555
Contextual Info: Third-Party Tool Support PRELIMINARY Support for Cypress programmable logic devices is available in many software products from third-party vendors. Some companies include support for the entire design process in products that they sell. Others provide software for a portion of

FLASH370I

Abstract: Ultra37032 FLASH370 UltraISRPCCABLE
Contextual Info: fax id: 6451 An Introduction to In-System Reprogramming ISR with the Ultra37000™ Introduction This application note provides an introduction to the Ultra37000™ family of In-System Reprogrammable (ISR™) CPLDs. The Ultra37000 ISR CPLD family upgrades the

schematic flash disk

Abstract: CY3140 ABEL
Contextual Info: PRELIMINARY CY3140 ABEL /Synario™ Design Kit for LASH370i™ Features System Requirements • Device independent design entry formats: — ABEL-HDL for ABEL-4, ABEL-5, and ABEL-6 — Schematic entry, VHDL, and ABEL-HDL for Synario™ • Full integration supporting all ABEL™ and Synario™

7C371-110

Abstract: 7C371-143 7C371-83 CY7C371 CY7C372 FLASH370
Contextual Info: For new designs see CY7C371i CY7C371 UltraLogic 32-Macrocell Flash CPLD Features • • • • • • of use and high performance of the 22V10 to high-density CPLDs. 32 macrocells in two logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins

Contextual Info: fax id: 6443 LASH370i 5V to 12V DC-DC Converter Solutions Introduction This application note provides various solutions for the 12V supervoltage requirement for our flash-based In-System Reprogrammable CPLDs in designs that do not already include a source for 12V.

CY37512

Contextual Info: UltraLogic 512-Macrocell ISR™ CPLD Features — tco = 6 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os

Contextual Info: Features « 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — fMAx = 100 MHz — tpo = 12 ns — ts = 7 ns " tco = 7 ns • Electrically Alterable Flash technology • Available in 84-pin PLCC, 84-pin

Contextual Info: CY7C372 PRELIMINARY CYPRESS 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed — fMAX - 125 MHz — tpD - 10 ns

S2112-05-ND

Abstract: cypress ultra37000 jtag FLASH370I 10-pin jtag
Contextual Info: 0i CY3600i LASH370i ISR™ Programming Kit Features • Supports LASH370i™ and Ultra37000™ devices for Ultra37000V 3.3V support, please see the Ultra37000 ISR™ Programming Kit data sheet, CY3700i • Jam programming language support for Ultra37000

3.3v to 5v buffer latch

Abstract: preset resistor 3.3v to 5v interface components
Contextual Info: fax id: 6136 PRELIMINARY CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks

tlO41

Abstract: 7C373-125 CY7C373 CY7C374 FLASH370 Wo2c
Contextual Info: CYPRESS Features • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — f M A X = 12S MHz — tpo = 10 ns — ts = 5.5 ns — tc o = 6-5 ns • Electrically alterable Flash

NCL025

Contextual Info: •■■■■■■\fct>cw.-. s a s iâ s ^ 5^” .w s & v PRELIMINARY _ . "T U ltra 3 7 5 1 2 UltraLogic 512-Macrocell ISR™ CPLD Features • • • • • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

Contextual Info: CY37192 UltraLogic 192-Macrocell ISR™ CPLD Features — tco = 4 .5 ns • Product-term clocking • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes

cypress flash 370

Abstract: 7C372 1603BB01932
Contextual Info: 40B-943-ZB43-> 07/31/95 09:03:11 1603BB0193Z Cypress Seniconducto Page B ll 7C372: Wednesday, September 23,1B62 Revision: Thursday, June 18,1B94 CYPRESS 64-Macrocell Flash CPLD Features FunctloDal Description e 64 macroceOs in four logic blocks The CY7C372li a F lu b erasable Complex

features cypress flash 370

Abstract: logic block diagram of cypress flash 370 device cypress flash 370 device cypress flash 370 cypress flash 370 technology cypress FLASH370 device cypress quickpro II cypress flash 370 device technology
Contextual Info: F la s h 3 7 0 T0 CYPRESS — Low-cost, text-based design tool, PLD compiler — IEEE 1076-compliant VHDL — Available on PC and Sun platforms • Warp3m CAE development system — VHDL input — ViewLogic graphical user interface — Schematic capture ViewDraw

CY7C371

Abstract: CY7C372 FLASH370
Contextual Info: For new designs see CY7C372i CY7C372 UltraLogic 64-Macrocell Flash CPLD Features • • • • • • of use and high performance of the 22V10 to high-density CPLDs. 64 macrocells in four logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins